STRUCTURE AND METHOD FOR A FISHBONE DIFFERENTIAL CAPACITOR

• US 20130228894A1
• Filed: 03/02/2012
• Published: 09/05/2013
• Est. Priority Date: 03/02/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yen, Hsiao-Tsung, Lin, Yu-Ling, Kuo, Chin-Wei, Chen, Ho-Hsiang, Jeng, Min-Chie
• Granted Patent: US 8,860,114 B2
• Time in Patent Office: Days
• US Class Current: 257/532
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 28/88 made by patterning layers, e.g. by etching conductive layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present disclosure provides an integrated circuit. The integrated circuit includes a substrate having a surface that is defined by a first axis and a second axis perpendicular to the first axis; and a capacitor structure disposed on the substrate. The capacitor structure includes a first conductive component; a second conductive component and a third conductive component symmetrically configured on opposite sides of the first conductive component. The first, second and third conductive components are separated from each other by respective dielectric material.

Claims

1. An integrated circuit, comprising:

a substrate having a surface that is defined by a first axis and a second axis perpendicular to the first axis; and

a capacitor structure disposed on the substrate, wherein the capacitor structure includes;

a first conductive component, and

a second conductive component and a third conductive component symmetrically configured on opposite sides of the first conductive component, wherein the first, second, and third conductive components are separated from each other by respective dielectric material.

2. The semiconductor structure of claim 1, wherein:

the first conductive component is configured to be connected to a first signal line; and

the second and third conductive components are configured to be connected to a second signal line.

3. The semiconductor structure of claim 1, wherein:

the first conductive component is configured to be connected to a first signal line;

the second conductive component is configured to be connected to a second signal line; and

the third conductive component is configured to be connected to a third signal line different from the second signal line.

4. The semiconductor structure of claim 3, wherein:

the first signal line is a ground line;

the second signal line is a power line of a first alternating current with a first magnitude and a first phase; and

the third signal line is another power line of a second alternating current with the first magnitude and a second phase opposite to the first phase.

5. The semiconductor structure of claim 1, wherein:

the first conductive component includes a first stem feature oriented in the first axis;

the second conductive component is disposed on a first side of the first conductive component and includes a plurality of first branch features oriented in the second axis; and

the third conductive component is disposed on a second side of the first conductive component and includes a plurality of second branch features oriented in the second axis.

6. The semiconductor structure of claim 5, wherein:

the second conductive component further includes a second stem feature oriented in the first axis and connected to the plurality of first branch features; and

the third conductive component further includes a third stem feature oriented in the first axis and connected to the plurality of second branch features.

7. The semiconductor structure of claim 6, wherein:

the first conductive component further includes a plurality of third branch features oriented in the first axis and connected to the first stem feature;

each of the third branch features includes a first segment extended to the first side and a second segment extended to the second side of the first stem feature; and

the third branch features are interdigitated with the first branch features on the first side and interdigitated with the second branch features on the second side.

8. The semiconductor structure of claim 1, further comprising an interconnect structure having a plurality of conductive layers on the substrate, wherein:

each of the conductive layers includes a plurality of conductive lines;

neighboring two of the conductive layers are connected through via features; and

the first, second, and third conductive components are distributed in the plurality of conductive layers and via features.

9. The semiconductor structure of claim 1, further comprising a first varactor and a second varactor formed on the substrate, wherein:

the first conductive component is connected to the first varactor; and

the second conductive component is connected to the second varactor.

10. The semiconductor structure of claim 1, further comprising:

a first shielding feature connected to the first conductive component; and

a second shielding feature connected to the second conductive component.

11. The semiconductor structure of claim 1, wherein the first, second, and third conductive components includes a conductive material selected from a group consisting of metal, metal alloy, metal silicide, and combinations thereof.

12. The semiconductor structure of claim 1, wherein:

the first conductive component includes a plurality of first features oriented in the first axis;

the second conductive component includes a plurality of second features oriented in the first axis;

the third conductive component includes a plurality of third features oriented in the first axis;

the plurality of second and third features are configured into pairs, wherein each pair includes one of the second features and one of the third features;

the one of the second features and the one of the third features in each pair are disposed in a same line oriented in the first axis; and

the first features are interdigitated with the pairs of the second and third features.

13. A semiconductor structure, comprising:

a substrate having a surface that is defined by a first axis and a second axis perpendicular to the first axis, wherein the substrate includes a first region, a second region, and a third region, wherein the first region is interposed between the second and third regions; and

a differential capacitor disposed on the substrate, wherein the differential capacitor includes;

a first conductive component having a first stem feature that is disposed in the first region,

a second conductive component disposed in the second region; and

a third conductive component disposed in the third region, wherein the second and third conductive components are symmetrically designed and symmetrically configured on opposite sides of the first conductive component.

14. The semiconductor structure of claim 13, wherein:

the first conductive component further includes a plurality of first branch features oriented in the second axis, connected to the first stem feature, and extended into the second region;

the first conductive component further includes a plurality of second branch features oriented in the second axis, connected to the first stem feature, and extended into the third region;

the second conductive component includes a second stem feature oriented in the first axis and a plurality of third branch features oriented in the second axis, the third branch features being connected to the second stem feature; and

the third conductive component includes a third stem feature oriented in the first axis and a plurality of fourth branch features oriented in the second axis, the fourth branch features being connected to the third stem feature.

15. The semiconductor structure of claim 14, wherein:

the first branch features are interdigitated with the third branch features in the second region; and

the second branch features are interdigitated with the fourth branch features in the third region.

16. The semiconductor structure of claim 15, wherein:

the first branch features are interdigitated with the third branch features along the first axis and a third axis that is perpendicular to the first axis and the second axis; and

the second branch features are interdigitated with the fourth branch features along the first axis and the third axis.

17. The semiconductor structure of claim 13, further comprising:

a first shielding feature disposed in the second region and connected to the second conductive component; and

a second shielding feature disposed in the third region and connected to the third conductive component.

18. The semiconductor structure of claim 17, further comprising a third shielding feature connected to the first conductive component and disposed in the first, second, and third regions, wherein the first, second, and third shielding features are configured such that:

the first and second shielding features are disposed on one side of the first, second, and third conductive components;

the third shielding feature is disposed on an opposite side of the first, second, and third conductive components; and

the first, second, and third conductive components are sandwiched by the first, second, and third shielding features.

19. The semiconductor device of claim 13, wherein:

the first, second, and third conductive components each include a plurality of metal lines, each metal line belonging to a different metal layer of an interconnect structure; and

a plurality of groups of metal vias, each group of metal vias interconnecting two of the plurality of metal lines along a third axis.

20. A method of fabricating an integrated circuit, comprising:

providing a substrate having a surface that is defined by a first axis and a second axis that is perpendicular to the first axis; and

forming an interconnect structure over the surface of the substrate, the interconnect structure having layers of conductive lines and levels of conductive vias interconnecting the layers of conductive lines, wherein the forming of the interconnect structure includes forming a capacitor structure disposed on the substrate, wherein the capacitor structure includes;

a first conductive component, and

a second conductive component and a third conductive component symmetrically configured on opposite sides of the first conductive component, wherein the first, second, and third conductive components are separated from each other by respective dielectric material.