MULTIPLE-INPUT AND MULTIPLE-OUTPUT CARRIER AGGREGATION RECEIVER REUSE ARCHITECTURE
First Claim
1. A wireless communication device configured for receiving a wireless multiple-input and multiple-output signal, comprising:
- a first multiple-input and multiple-output carrier aggregation receiver reuse architecture that comprises;
a first antenna;
a second antenna; and
a transceiver chip, wherein the first multiple-input and multiple-output carrier aggregation receiver reuse architecture reuses a first carrier aggregation receiver path; and
a second multiple-input and multiple-output carrier aggregation receiver reuse architecture that comprises;
a third antenna;
a fourth antenna; and
a receiver chip, wherein the second multiple-input and multiple-output carrier aggregation receiver reuse architecture reuses a second carrier aggregation receiver path.
1 Assignment
0 Petitions
Accused Products
Abstract
A wireless communication device configured for receiving a wireless multiple-input and multiple-output signal. The wireless communication device includes a first multiple-input and multiple-output carrier aggregation receiver reuse architecture. The first multiple-input and multiple-output carrier aggregation receiver reuse architecture includes a first antenna, a second antenna and a transceiver chip. The first multiple-input and multiple-output carrier aggregation receiver reuse architecture reuses a first carrier aggregation receiver path. The wireless communication device also includes a second multiple-input and multiple-output carrier aggregation receiver reuse architecture. The second multiple-input and multiple-output carrier aggregation receiver reuse architecture includes a third antenna, a fourth antenna and a receiver chip. The second multiple-input and multiple-output carrier aggregation receiver reuse architecture reuses a second carrier aggregation receiver path.
-
Citations
35 Claims
-
1. A wireless communication device configured for receiving a wireless multiple-input and multiple-output signal, comprising:
-
a first multiple-input and multiple-output carrier aggregation receiver reuse architecture that comprises; a first antenna; a second antenna; and a transceiver chip, wherein the first multiple-input and multiple-output carrier aggregation receiver reuse architecture reuses a first carrier aggregation receiver path; and a second multiple-input and multiple-output carrier aggregation receiver reuse architecture that comprises; a third antenna; a fourth antenna; and a receiver chip, wherein the second multiple-input and multiple-output carrier aggregation receiver reuse architecture reuses a second carrier aggregation receiver path. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
-
-
14. A method for receiving a multiple-input and multiple-output wireless signal, comprising:
-
receiving a first multiple-input and multiple-output wireless signal using a first antenna; routing the first multiple-input and multiple-output wireless signal through a first primary receiver on a transceiver chip to obtain a primary receive inphase/quadrature signal; receiving a second multiple-input and multiple-output wireless signal using a second antenna; routing the second multiple-input and multiple-output wireless signal through a first secondary receiver on the transceiver chip to obtain a secondary receive inphase/quadrature signal; receiving a third multiple-input and multiple-output wireless signal using a third antenna; routing the third multiple-input and multiple-output wireless signal through a second primary receiver on a receiver chip to obtain a tertiary receive inphase/quadrature signal; receiving a fourth multiple-input and multiple-output wireless signal using a fourth antenna; and routing the fourth multiple-input and multiple-output wireless signal through a second secondary receiver on the receiver chip to obtain a quaternary receive inphase/quadrature signal. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
-
-
31. An apparatus for receiving a multiple-input and multiple-output wireless signal, comprising:
-
means for receiving a first multiple-input and multiple-output wireless signal; means for routing the first multiple-input and multiple-output wireless signal through a first primary receiver on a transceiver chip to obtain a primary receive inphase/quadrature signal; means for receiving a second multiple-input and multiple-output wireless signal; means for routing the second multiple-input and multiple-output wireless signal through a first secondary receiver on the transceiver chip to obtain a secondary receive inphase/quadrature signal; means for receiving a third multiple-input and multiple-output wireless signal; means for routing the third multiple-input and multiple-output wireless signal through a second primary receiver on a receiver chip to obtain a tertiary receive inphase/quadrature signal; means for receiving a fourth multiple-input and multiple-output wireless signal; and means for routing the fourth multiple-input and multiple-output wireless signal through a second secondary receiver on the receiver chip to obtain a quaternary receive inphase/quadrature signal. - View Dependent Claims (32, 33, 34, 35)
-
Specification