Trench Electrode Arrangement

• US 20130230956A1
• Filed: 03/25/2013
• Published: 09/05/2013
• Est. Priority Date: 09/23/2011
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Meiser, Andreas, Schloesser, Till, Zundel, Markus
• Granted Patent: US 9,324,829 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method includes forming a trench extending from a first surface of a semiconductor body into the semiconductor body such that a first trench section and at least one second trench section adjoin the first trench section, wherein the first trench section is wider than the second trench section. A first electrode is formed, in the at least one second trench section, and dielectrically insulated from semiconductor regions of the semiconductor body by a first dielectric layer. An inter-electrode dielectric layer is formed, in the at least one second trench section, on the first electrode. A second electrode is formed, in the at least one second trench section on the inter-electrode dielectric layer, and in the first trench section, such that the second electrode at least in the first trench section is dielectrically insulated from the semiconductor body by a second dielectric layer.

Claims

1. A method for producing a semiconductor device, the method comprising:

forming a trench extending from a first surface of a semiconductor body into the semiconductor body such that the trench has a first trench section and at least one second trench section adjoining the first trench section, and wherein the trench is wider in the first trench section than in the second trench section;

forming, in the at least one second trench section, a first electrode dielectrically insulated from semiconductor regions of the semiconductor body by a first dielectric layer;

forming, in the at least one second trench section, an inter-electrode dielectric layer on the first electrode; and

forming, in the at least one second trench section on the inter-electrode dielectric layer, and in the first trench section, a second electrode, such that the second electrode at least in the first trench section is dielectrically insulated from semiconductor regions of the semiconductor body by a second dielectric layer.

2. The method of claim 1, wherein the trench is formed such that, in the wider trench section, the trench extends deeper into the semiconductor body than in the narrower trench section.

3. The method of claim 1, further comprising:

forming the second electrode in the first trench section such that the second electrode is dielectrically insulated from semiconductor regions of the semiconductor body by a third dielectric layer on sidewalls of the first trench section.

4. The method of claim 1, further comprising:

forming the inter-electrode dielectric on a bottom of the first trench section.

5. The method of claim 1, wherein the trench is formed such that a width of the trench gradually increases from a first width in the at least one second trench section to a second width in the first trench section, wherein the second width is larger than the first width.

6. The method of claim 1, further comprising:

exposing a section of the second electrode arranged in the first trench section on a second surface opposite the first surface of the semiconductor body.

7. The method of claim 1, wherein forming the trench comprises forming two second trench sections adjoining the first trench section on opposite sides.

8. The method of claim 1, wherein forming the first electrode in the at least one second trench section comprises:

forming the first dielectric layer on a bottom of the at least one second trench section and on sidewalls at least in a lower portion of the at least one second trench section;

forming a first electrode layer in the first trench section and the at least one second trench section such that the first electrode layer leaves a residual trench in the first trench section and completely fills the trench in the at least one second trench section;

removing the first electrode layer in the first trench section; and

partially removing the first electrode layer in the at least one second trench section such that the first electrode layer remains in the lower portion of the at least one second trench section.

9. The method of claim 1, further comprising:

forming the inter-electrode dielectric layer on the bottom of the first trench section.

10. The method of claim 1, further comprising:

forming a third dielectric layer on sidewalls of the first trench section after forming the inter-electrode dielectric layer.

11. The method of claim 10, wherein at least a part of the third dielectric layer is formed simultaneously while forming the second dielectric layer.

12. The method of claim 1, further comprising:

forming, in the semiconductor body, a body region adjacent the second dielectric layer in the at least one second trench section;

forming a source region in the body region and adjacent the second dielectric layer.

13. The method of claim 1, further comprising:

electrically connecting a first device structure to the first electrode at a first position of the first electrode, and a second device structure to the first electrode at a second position distant to the first position of the first electrode;

electrically connecting a third device structure to the second electrode at a first position of the first electrode, and a fourth device structure to the first electrode at a second position distant to the first position of the second electrode.

14. The method of claim 13, wherein at least one of the first device structure, the second device structure, the third device structure, and the fourth device structure, is selected from one of:

a doped semiconductor region;

an electrically conducting contact; and

a connection line.