Semiconductor Devices and Methods of Manufacture Thereof

• US 20130234203A1
• Filed: 03/08/2012
• Published: 09/12/2013
• Est. Priority Date: 03/08/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tsai, Ji-Yin, Huang, Yao-Tsung, Ko, Chih-Hsin, Wann, Clement Hsingjen
• Granted Patent: US 8,785,285 B2
• Time in Patent Office: Days
• US Class Current: 257/190
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a channel region in a workpiece, and forming a source or drain region proximate the channel region. The source or drain region includes a contact resistance-lowering material layer comprising SiP, SiAs, or a silicide. The source or drain region also includes a channel-stressing material layer comprising SiCP or SiCAs.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

forming a channel region in a workpiece; and

forming a source or drain region proximate the channel region, wherein the source or drain region includes a contact resistance-lowering material layer comprising SiP, SiAs, or a silicide, and wherein the source or drain region includes a channel-stressing material layer comprising SiCP or SiCAs.

2. The method according to claim 1, wherein forming the source or drain region comprises forming the contact resistance-lowering material layer over the channel-stressing material layer.

3. The method according to claim 1, wherein forming the source or drain region comprises forming the channel-stressing material layer over the contact resistance-lowering material layer.

4. The method according to claim 3, wherein forming the contact resistance-lowering material layer comprises forming a first contact resistance-lowering material layer, further comprising forming a second contact resistance-lowering material layer over the channel-stressing material layer.

5. The method according to claim 1, wherein forming the channel region comprises forming SiGe or a III-V material.

6. The method according to claim 1, wherein forming the contact resistance-lowering material layer or the channel-stressing material layer does not include an implantation process or an anneal process.

7. The method according to claim 1, wherein forming the source or drain region comprises recessing the workpiece proximate the channel region using an etch process, and forming the contact resistance-lowering material layer and the channel-stressing material layer in the recess.

8. The method according to claim 7, wherein the etch process comprises an anisotropic component.

9. The method according to claim 1, wherein forming the source or drain region comprises forming a source or drain region that is spaced apart from the channel region by about 20 nm or less at a widest point of the source or drain region.

10. A method of manufacturing a semiconductor device, the method comprising:

providing a workpiece;

forming a channel region in the workpiece;

forming a gate dielectric over the channel region;

forming a gate over the gate dielectric; and

forming a source region and a drain region proximate the channel region, the source region and the drain region including a contact resistance-lowering material layer comprising SiP, SiAs, or a silicide, and the source region and the drain region including a channel-stressing material layer comprising SiCP or SiCAs.

11. The method according to claim 10, wherein forming the semiconductor device comprises forming a fin field effect transistor (FinFET) or a planar transistor.

12. The method according to claim 10, wherein forming the source region and the drain region comprise forming recesses in the workpiece, further comprising:

forming a first liner on bottom surfaces of the recesses; and

forming a second liner on sidewalls of the recesses.

13. The method according to claim 12, wherein forming the first liner comprises forming SiP, and wherein forming the second liner comprises forming SiAs.

14. The method according to claim 10, wherein forming the source region and the drain region comprises using AsH₃ as a dopant gas.

15. A semiconductor device, comprising:

a transistor including;

a channel region disposed in a workpiece;

a gate dielectric disposed over the channel region;

a gate disposed over the gate dielectric; and

a source region and a drain region proximate the channel region, the source region and the drain region including;

a contact resistance-lowering material layer comprising SiP, SiAs, or a silicide; and

a channel-stressing material layer comprising SiCP or SiCAs.

16. The semiconductor device according to claim 15, wherein the channel region comprises a fin of semiconductive material.

17. The semiconductor device according to claim 16, wherein the source or drain region is disposed in a recess in the workpiece proximate the fin of semiconductive material.

18. The semiconductor device according to claim 17, wherein the fin comprises a height comprising a first dimension within the workpiece, wherein the recess comprises a depth comprising a second dimension, and wherein the second dimension comprises about twice the first dimension or greater.

19. The semiconductor device according to claim 18, wherein the contact resistance-lowering material layer is disposed over the channel-stressing material layer, and wherein the second dimension comprises about thrice the first dimension or greater.

20. The semiconductor device according to claim 19, wherein a boundary between the contact resistance-lowering material layer and the channel-stressing material layer is disposed proximate a bottom of the channel region.