SEMICONDUCTOR DEVICE HAVING JUNCTIONLESS VERTICAL GATE TRANSISTOR AND METHOD OF MANUFACTURING THE SAME

• US 20130234240A1
• Filed: 02/05/2013
• Published: 09/12/2013
• Est. Priority Date: 03/12/2012
• Status: Active Grant

• Current Assignee: Korea Advanced Institute of Science and Technology, SK Hynix Inc.
• Original Assignee: Korea Advanced Institute of Science and Technology, SK Hynix Inc.
• Inventors: MOON, Jung-Min, KIM, Tae-Kyun, LEE, Seok-Hee
• Granted Patent: US 9,136,376 B2
• Time in Patent Office: Days
• US Class Current: 257/329
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line

Abstract

A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity.

Claims

1. A semiconductor device comprising:

an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region over the first impurity region, and a third impurity region over the second impurity region formed ;

a gate electrode formed over a sidewall of the second impurity region; and

a bit line arranged in a cross direction from the gate electrode and contacted to the first impurity region,

wherein the first, second, and third impurity regions comprise impurities of the same polarity.

2. The semiconductor device according to claim 1, wherein each of the first, second, and third impurity regions has an impurity concentration ranging from 8×

1018 to 3×

1019 atom/cm3.

3. The semiconductor device according to claim 1, wherein the first, second, and third impurity regions have substantially the same impurity concentration.

4. The semiconductor device according to claim 1, wherein the first impurity region is a drain region, the second impurity region is a body region, and the third impurity region is a source region.

5. The semiconductor device according to claim 1, wherein the gate electrode surrounds the sidewall of the second impurity region.

6. The semiconductor device according to claim 1, wherein the bit line is contact a sidewall of the first impurity region and is formed over the substrate.

7. The semiconductor device according to claim 1, wherein the bit line is formed in the substrate and under the first impurity region, wherein the bit line is contacted to a bottom of the first impurity region.

8. The semiconductor device according to claim 7, the device further comprising:

an insulation layer formed between the substrate and the bit line.

9. The semiconductor device according to claim 1, wherein the substrate is a silicon (Si) substrate, and the active pillar comprises an N-type impurity.

10. The semiconductor device according to claim 1, wherein the substrate is any of a Si—

Ge substrate, a Ge substrate, a III-V group compound semiconductor substrate and a combination thereof, and the active pillar comprises a P-type impurity.

11. The semiconductor device according to claim 1, wherein the substrate has a nano structure, wherein the nano structure includes any of a nano wire structure, a nano ribbon structure, and a combination thereof.

12. The semiconductor device according to claim 1, the device further comprising:

a gate insulation layer,

wherein the gate insulation layer comprises;

a vertical insulation section formed between the gate electrodes and the second impurity region, and

a horizontal insulation section contacted to a lower portion of the vertical insulation section and formed between the first impurity region and the gate electrodes,

wherein the horizontal insulation section is thicker than the vertical insulation section.

13. A method of manufacturing a semiconductor device, comprising:

forming a plurality of active pillars, each having a first impurity region formed over a substrate and second and third impurity regions sequentially formed on the first impurity region;

forming a bit line between adjacent active pillars and over the substrate to be insulated from the substrate and contacting to a first sidewall of the first impurity region; and

forming a gate electrode over a sidewall of the second impurity region in a direction of intersecting with the bit line.

14. The method according to claim 13, wherein forming the gate electrode comprises:

forming an insulation layer over the bit line;

patterning the insulation layer and the plurality of active pillars to form a plurality of trenches, each of the trenches extending in a cross direction from the bit line;

forming a gate insulation layer over a bottom surface and a sidewall of the trench; and

forming the gate electrode with a conductive material over the gate insulation layer to be disposed over the sidewall of the second impurity region.

15. The method according to claim 13, wherein the step of forming the plurality of active pillars comprises:

activating the first impurity region; and

activating the second impurity region and the third impurity region,

wherein the first, second, and third impurity regions are performed using an in-situ process.

16. The method according to claim 13, wherein the step of forming the plurality of active pillars comprises:

forming a semiconductor growth layer including first, second, and third region layers over the substrate;

implanting impurities with substantially the same polarity into the first, second, and third region layers of the semiconductor growth layer; and

patterning the impurity-implanted semiconductor growth layer to form the plurality of active pillars.

17. The method according to claim 13, wherein forming the plurality of active pillars comprises:

stacking a semiconductor substrate including first, second, and third impurity regions over the substrate; and

patterning the semiconductor substrate to form the plurality of active pillars.

18. The method according to claim 13, wherein the first, second, and to third impurity regions have substantially the same impurity concentration.

19. The method according to claim 13, wherein the plurality of active pillars are formed by using any of multi ion implantation, tilt ion implantation, and orient ion implantation.

20. The method according to claim 13, wherein forming the bit line comprises:

forming an insulation layer over a second sidewall of the first impurity region and over the substrate between adjacent active pillars; and

forming a conductive material layer over the insulation layer to obtain the bit line.