SHIELDED GATE MOSFET DEVICE WITH A FUNNEL-SHAPED TRENCH

• US 20130234241A1
• Filed: 03/09/2012
• Published: 09/12/2013
• Est. Priority Date: 03/09/2012
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Bowers, Brian
• Granted Patent: US 8,816,431 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A MOSFET device has a funnel-shaped trench etched in a semiconductor substrate. The funnel-shaped trench has flared rim extending from a wider cross section trench mouth at the surface of the semiconductor substrate to a narrower cross section trench body portion which terminates in an epilayer portion of the semiconductor substrate. A gate electrode is disposed in the trench on the flared rim. Source and gate regions of the device abut upper and lower portions of the flared rim, respectively. A drain region of the device, which abuts the narrower cross section trench body portion, is self-aligned with a lower edge of a gate electrode.

Claims

1. A metal-oxide-semiconductor field-effect transistor (MOSFET) device, comprising:

a funnel-shaped trench having a flared rim etched in a semiconductor substrate,

the flared rim having an upper edge at a wider cross section trench opening at about a top surface of the semiconductor substrate and a lower edge at a top opening of a narrower cross section trench body portion that terminates in the semiconductor substrate;

a gate electrode disposed in the funnel-shaped trench on a gate oxide layer formed on the flared rim; and

source, gate and drain regions formed in the semiconductor substrate,

the gate region abutting the flared rim, the drain region abutting sidewalls of the narrower cross section trench body portion with a top of the drain region being aligned with a lower edge of the gate electrode.

2. The MOSFET device of claim 1, wherein the flared rim has a substantially linear profile in cross-section between its upper edge and its lower edge.

3. The MOSFET device of claim 1, wherein the flared rim has a curved profile in cross-section between its upper edge and its lower edge.

4. The MOSFET device of claim 1, wherein the flared rim is flared at an angle of about 45 degrees to a perpendicular to the top surface of the semiconductor substrate.

5. The MOSFET device of claim 1, wherein the flared rim is flared at an angle of between 20 degrees and 80 degrees to a perpendicular to the surface of the semiconductor substrate.

6. The MOSFET device of claim 1, wherein the lower edge of the gate electrode is at about the lower edge of the flared rim.

7. The MOSFET device of claim 1, wherein the gate electrode includes one or more of polysilicon, cobalt silicide and titanium silicide materials.

8. The MOSFET device of claim 1, wherein the funnel-shaped trench has a depth greater than about 1 μ

m.

9. The MOSFET device of claim 1, wherein the trench opening at the surface of the semiconductor substrate has a width in the range of about 0.5 μ

m to 4.0 μ

m.

10. The MOSFET device of claim 1, wherein the top opening of the narrower cross section trench body portion has a width in the range of about 0.2 μ

m to 3.0 μ

m.

11. The MOSFET device of claim 1, further comprising a shield gate electrode disposed in the narrower cross section trench body portion, the shield gate electrode being insulated from and disposed below the gate electrode.

12. The MOSFET device of claim 1, further comprising a self-aligned source-metal contact.

13. The MOSFET device of claim 1, wherein the semiconductor substrate is a heavily doped n-type conductive substrate with a lightly doped n-type epitaxial silicon over layer, and wherein the funnel-shaped trench terminates within the epitaxial silicon over layer.

14. The MOSFET device of claim 1, wherein the semiconductor substrate is a heavily doped p-type conductive substrate with a lightly doped p-type epitaxial silicon over layer, and wherein the funnel-shaped trench terminates within the epitaxial silicon over layer.

15. A method, comprising:

forming a trench in a semiconductor substrate, the trench having a flared rim, the flared rim extending down from a wider cross-section trench opening at about a top surface of the semiconductor substrate to a narrower cross-section trench body portion that terminates in the semiconductor substrate;

disposing, in the trench, a gate electrode on the flared rim;

forming a drain region in the semiconductor substrate, the drain region having its top aligned with about a lower edge of the gate electrode disposed on the flared rim;

forming a gate region in the semiconductor substrate above the drain region; and

forming a source region in the semiconductor substrate above the gate region.

16. The method of claim 15, wherein forming a trench in the semiconductor substrate includes:

dry etching the semiconductor substrate using halogen-based chemistries; and

shaping the trench to have a flared rim as it is being etched by adjusting etch bias and selectivity during the dry etching.

17. The method of claim 15, wherein disposing a gate electrode on the flared rim includes disposing a polysilicon electrode on a gate oxide layer formed on the flared rim.

18. The method of claim 15, wherein forming the drain region having its top aligned with about the lower edge of the gate electrode includes:

introducing dopants in a region of the semiconductor substrate abutting the narrow cross section trench body portion; and

disposing masking material on the flared rim to block introduction of dopants in a region of the semiconductor substrate abutting the flared rim.

19. The method of claim 18, wherein the introducing dopants in the region of the semiconductor substrate abutting the narrower trench body includes implanting ions at an angle through a sidewall of the trench.

20. The method of claim 18, wherein the introducing dopants in the region of the semiconductor substrate abutting the narrow trench body includes diffusing dopants through the sidewall of the trench.

21. The method of claim 15, wherein forming a source region above the gate region includes introducing dopants in portions of the semiconductor substrate above a top edge of the gate electrode.

22. A metal-oxide-semiconductor field-effect transistor (MOSFET) device, comprising:

a funnel-shaped trench etched in a semiconductor substrate, the funnel-shaped trench having a flared rim and having a trench body disposed below the flared rim, the flared rim having a sidewall with a first slope and the trench body having a sidewall with a second slope different from the first slope;

a gate oxide layer disposed in the trench on the flared rim;

a gate electrode disposed on the gate oxide layer;

a source region abutting an upper portion of the flared rim;

a gate region abutting a lower portion of the flared rim; and

a drain region abutting sidewalls of the trench body, the drain region having a top aligned with a lower edge of the gate electrode.

23. The MOSFET device of claim 22, wherein the first slope is about 45 degrees to a perpendicular to a top surface of the semiconductor substrate.

24. The MOSFET device of claim 22, wherein the first slope is about between 20 degrees and 80 degrees to a perpendicular to a surface of the semiconductor substrate.

25. The MOSFET device of claim 22, wherein the lower edge of the gate electrode is at about the lower edge of the flared rim.

26. The MOSFET device of claim 22, wherein the gate electrode includes one or more of a polysilicon material, cobalt silicide and titanium silicide.

27. The MOSFET device of claim 22, further comprising a shield gate electrode disposed in the trench body below the flared rim, the shield gate electrode insulated from the gate electrode.

28. The MOSFET device of claim 22, wherein the semiconductor substrate is a heavily doped n-type conductive substrate with a lightly doped n-type epitaxial silicon over layer, and wherein the funnel-shaped trench terminates within the epitaxial silicon over layer.

29. The MOSFET device of claim 22, wherein the semiconductor substrate is a heavily doped p-type conductive substrate with a lightly doped p-type epitaxial silicon over layer, and wherein the funnel-shaped trench terminates within the epitaxial silicon over layer.