METHOD FOR TESTING COMPARATOR AND DEVICE THEREFOR

• US 20130234743A1
• Filed: 03/07/2012
• Published: 09/12/2013
• Est. Priority Date: 03/07/2012
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Ren, Juxiang, Dao, Chris C., Pietri, Stefano
• Granted Patent: US 9,134,395 B2
• Time in Patent Office: Days
• US Class Current: 324/750.02
• CPC Class Codes: G01R 31/3163 Functional testing
• CPC Class Codes: G01R 31/3167 Testing of combined analog and digital circuits testing ADC's H03M1/1071
• CPC Class Codes: G01R 31/31703 Comparison aspects, e.g. signature analysis, comparators concerning scan tests G01R31/318566; concerning testers G01R31/3193
• CPC Class Codes: G01R 35/00 Testing or calibrating of apparatus covered by the other groups of this subclass
• CPC Class Codes: H03K 5/24 the characteristic being amplitude

Abstract

An integrated circuit facilitates a self test routine that verifies proper operation of an analog comparator. In response to entering the self test routine, the voltage provided to an input of a comparator is changed from being at an operating voltage supply to being at a self test voltage that is used to verify operation of the comparator. In response to the comparator operating properly, the self test voltage provided to the input of the comparator is replaced with the operating voltage supply, and normal operation resumes. The duration of the self test cycle is based upon the amount of time during which the self test voltage is provided to the comparator is asynchronous in nature, and therefore not a function of a clock signal.

Claims

1. A method comprising:

comparing with a comparator a first voltage used to power a set of devices at an integrated circuit to a first reference voltage;

determining, based upon the comparison, that the first voltage meets an operating criteria;

entering a self-test mode of operation from a first mode of operation responsive to receiving a first self-test indicator;

responsive to entering the self-test mode of operation, testing the comparator to verify that the comparator is operational to detect a violation of the operating criteria when the test generates a test state at the output of the comparator; and

in response to determining the comparator is operational, returning to the first mode of operation asynchronously.

2. The method of claim 1 further comprising:

providing the first voltage to a first input of a multiplexor;

providing a second reference voltage to a second input of the multiplexor; and

wherein testing comprises selecting the second input of the multiplexor to provide the second reference voltage to the comparator instead of the first voltage.

3. The method of claim 2, wherein the second reference voltage is within 300 millivolts of the first reference voltage, wherein the first reference voltage is between the first voltage and the second reference voltage.

4. The method of claim 1 further comprising providing the self-test indicator in response to determining an indicator at a programmable storage location that enables self test has been asserted.

5. The method of claim 1, further comprising:

providing the self-test indicator in response to determining an indicator at a programmable storage location that enables self test has been asserted, wherein only one the first self-test indicator is asserted in response to the indicator at the programmable storage location being asserted.

6. The method of claim 1, further comprising:

providing the self-test indicator in response to determining an indicator at a programmable storage location that enables self test has been asserted, wherein a plurality of self-test indicators, including the first self-test indicator, are providing on a periodic interval in response to the indicator at the programmable storage location being asserted.

7. The method of claim 6, wherein a duration of the periodic interval is based upon a value stored at a second programmable storage location.

8. The method of claim 1, wherein returning to the first mode of operation occurs within 300 ns of entering the self-test mode of operation.

9. The method of claim 1 further comprising:

generating the first voltage reference and the second voltage reference based on a bandgap reference.

10. The method of claim 9, wherein no common circuitry is used to generate the first voltage reference and the second voltage reference based on the band gap reference.

11. The method of claim 9, wherein the first voltage reference and the second voltage reference are generated by substantially the same circuitry.

12. The method of claim 1 further comprising:

providing an asserted self-test result indicator in response to determining the comparator is operational, otherwise, providing a negated self-test result indicator in response to determining the comparator is not operational.

13. A device comprising:

a comparator comprising a first comparator input, a second comparator input, and a comparator output;

a selection circuit comprising a first data input, a second data input, a select input and an output coupled to the first input of the comparator, the first input to receive a first voltage identifying a first extreme voltage of an operational voltage range, the second input coupled to receive a second voltage, the first extreme voltage between the first voltage and a second extreme voltage of the operational voltage range; and

a delay path between the output of the comparator and the select input of the multiplexor that asynchronously selects select the first data input of the multiplexor responsive to the second input being previously selected.

14. The device of claim 13 wherein the asynchronous delay path comprises:

control logic having a first input to receive a self-test indicator, a second input to receive a signal communicated from the output of the comparator, and an output to provide a first select signal to switch from selecting the first input to selecting the second data input of the multiplexer in response to receiving an asserted self-test indicator at the first input, and to asynchronously provide a second select signal to switch from selecting the second data input to selecting the first data input of the multiplexer in response to the comparator providing a signal that indicates the first voltage reference is outside the operational voltage range.

15. The device of claim 13 further comprising:

a first programmable location to store a first indicator; and

a control logic that comprises the delay path having a first input coupled to the first programmable storage location, a second input coupled to the output of the comparator, and an output to provide a select signal to select the second data input of the multiplexor responsive to a state of the first indicator, and to subsequently provide the select signal to select the first input responsive to a change of state at the output of the comparator occurring responsive to providing the second reference voltage to the comparator.

16. The device of claim 13, wherein the delay path includes self-test control logic to verify proper operation of the comparator in response to the second input being selected.

17. The device of claim 16, wherein the self-test control logic is to periodically verify proper operation of the comparator in response to a first programmable location storing a first indicator.

18. The device of claim 13, wherein the self-test control logic is to verify proper operation of the comparator only one time in response to a first programmable location storing a first indicator.

19. A method comprising:

providing a first voltage to a set of devices that are to operate within a first voltage range defined by a first trip voltage and a second trip voltage;

providing by a first select circuit the first voltage to a first input of a first comparator;

providing the first trip voltage to a second input of the first comparator;

providing a first state at an output of the first comparator while providing the first voltage and the first trip voltage to the first comparator, the first state at the second comparator indicative of the first voltage meeting the an operating criteria defined by the first trip voltage;

at a first time, switching from providing by the select circuit the first voltage to providing a first self-test voltage to the first input of the first comparator, the first self test being outside of the first voltage range;

responsive to providing the first self-test voltage, determining whether the output of the first comparator is at a second state; and

responsive to the output of the comparator being in the second state, and independent of any user software intervention, switching the select circuit from providing the first self-test voltage to providing the first voltage to the first input of the first comparator.

20. The method of claim 19 further comprising:

providing by a second select circuit the first voltage to a first input of a second comparator;

providing the second trip voltage to a second input of the second comparator;

providing the first state at an output of the second comparator while providing the first voltage and the second trip voltage to the first comparator, the first state at the second comparator indicative of the first voltage meeting the an operating criteria defined by the first trip voltage; and

at a second time, switching from providing by the second select circuit the first voltage to providing a second self-test voltage to the first input of the second comparator, the second self-test voltage being between outside first voltage range.