Systems and Methods for Temporarily Retiring Memory Portions

• US 20130238839A1
• Filed: 10/11/2012
• Published: 09/12/2013
• Est. Priority Date: 12/05/2007
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: DensBits Technologies Ltd. (Broadcom, Inc.)
• Inventors: Weingerten, Hanan, Levy, Shmuel, Katz, Michael
• Granted Patent: US 8,843,698 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

A flash memory apparatus that may include a plurality of memory portions, and a controller operative to reserve for data retention purposes, for at least a first duration of time, only certain memory portions; allocate data, during said first duration of time, only to said certain memory portions, thereby to define a retired memory portion for said first duration of time; determine to copy data from a certain memory portion to a retired memory portion based upon a relationship between effective cycle counts of the certain memory portion and the retired memory portion, an effective cycle count of any memory portion is responsive to a number of erase-write cycles and to an effective duration of time the memory portion had available to recover from erase-write cycles; and copy the data from the certain memory portion to the retired memory portion.

Claims

1. Flash memory apparatus including:

a plurality of memory portions, and a controller operative to;

reserve for data retention purposes, for at least a first duration of time, only certain memory portions from among said plurality of memory portions;

allocate data, during said first duration of time, only to said certain memory portions, thereby to define at least one of the plurality of memory portions other than to said certain portions as a retired memory portion for said first duration of time;

determine to copy data from a certain memory portion of said certain memory portions to a retired memory portion based upon a relationship between an effective cycle count of the certain memory portion and an effective cycle count of the retired memory portion;

wherein an effective cycle count of an memory portion is responsive to a number of erase-write cycles that the memory portion has undergone and to an effective duration of time the memory portion had available to recover from erase-write cycles it has undergone; and

copy the data from the certain memory portion to the retired memory portion.

2. The flash memory apparatus according to claim 1 wherein said controller is operative to program incoming data, for said first duration of time, only into said certain portions.

3. The flash memory apparatus according to claim 1 wherein said controller is operative to read data, for said first duration of time, only from said certain portions.

4. The flash memory apparatus according to claim 1 wherein said controller is arranged to estimate the first duration on time in response to erase requests to erase the plurality of memory portions in their entirety or to requests to write requests the plurality of memory portions in their entirety.

5. The flash memory apparatus according to claim 1 wherein said controller is operative at least once to define said at least one retired memory portion as an active memory portion in which data can be stored, by including said retired memory portion in said certain portions after said first duration of time has elapsed so as to reserve for data retention purposes, for at least a second duration of time subsequent to said first duration of time, only said certain portions, thereby to benefit from enhanced data retention performance of said retired memory portion due to retirement thereof during said first duration.

6. The flash memory apparatus according to claim 5 wherein at least one said retired memory portions defined as an active portion was, before becoming a retired memory portion for time period T, defined as one of said certain memory portions and wherein the controller is operative to erase said memory portion defined as one of said certain memory portions, then as a retired memory portion, then again as an active memory portion, within said time period T.

7. The flash memory apparatus according to claim 1 wherein said controller is operative to retire memory portions in order of an importance of data stored in the memory portions.

8. The flash memory apparatus according to claim 7 wherein said controller serves a data-employing application and wherein at least said individual one of said memory portions defined as a retired portion comprises a memory portion from among said certain memory portions which contains data no longer needed by said data-employing application.

9. The flash memory apparatus according to claim 8 wherein said controller is operative to define at least said individual one of said certain memory portions as a retired portion, subsequent to receipt of an erase command pertaining to said at least one individual memory portion.

10. The flash memory apparatus according to claim 7 wherein the controller is operative to reproduce data from at least said individual memory portion defined as a retired portion, in an additional memory portion from among said plurality of memory portions.

11. The flash memory apparatus according to claim 10 wherein said additional memory portion comprises a formerly retired portion which is re-defined by the controller after said first duration as a newly active portion by reserving said formerly retired portion for data retention purposes after said first duration, while defining said newly active memory, portion as a retired portion which is not reserved for data retention purposes after said first duration.

12. The flash memory apparatus according to claim 1 wherein a population of traps develops in said memory portions responsive to cycling thereof and subsides between cycles as a function of time between said cycles, and wherein said first duration of time for which at least one individual memory portion is retired is selected to statistically contain increase in said population of traps in said individual memory portion.

13. The flash memory apparatus according to claim 12 wherein said plurality of memory portions comprise NROM flash memory portions.

14. The flash memory apparatus according to claim 12 wherein said first duration of time for which at least one individual memory portion is retired is selected to statistically prevent increase in said population of traps in said individual memory portion.

15. The flash memory apparatus according to claim 1 and also comprising a heating system heating at least one retired memory portion.

16. The flash memory apparatus according to claim 1 wherein a population of traps develops in said memory portions responsive to cycling thereof and subsides between cycles as a function of time between said cycles, the apparatus also comprising an effective cycle counter for at least an individual memory portion from among said certain memory portions, operative to store an effective number of cycles which said individual memory portion has undergone, wherein said effective number is an increasing function of an actual number of cycles that said individual memory portion has undergone and a decreasing function of a length of at least one time period extending between cycles that said individual memory portion has undergone.

17. The flash memory apparatus according to claim 16 wherein said plurality of memory portions comprises a number of sets of NAND flash memory cells strung together into a corresponding number of strings of cells and wherein said heating system comprises an apparatus for selectively heating a selected one of said strings of cells without beating another of said strings of cells.

18. The flash memory apparatus according to claim 1 wherein the controller, at intervals, re-defines at least one memory portion having one status from among an active status and a retired status, to another status from among said active status and said retired status, and wherein said intervals are periodical.

19. The flash memory apparatus according to claim 1 wherein the controller, at intervals, re-defines at least one memory portion having one status from among an active status and a retired status, to another status from among said active status and said retired status, and wherein said intervals are triggered by occurrence of a flash memory event.

20. The flash memory apparatus according to claim 19 wherein said flash memory event comprises issuance of an erase command to at least one of said plurality of memory portions.

21. The flash memory apparatus according to claim 1 wherein the controller, at intervals, re-defines at least one retired memory portion as an active memory portion reserved for data retention purposes, and wherein a redundant code characterized by a proportion of redundancy is used to encode said plurality of memory portions and wherein said proportion of redundancy is selected to take into account a reduced probability of error in said retired memory portion redefined as an active memory portion.

22. The flash memory apparatus according to claim 1 wherein said controller is operative, for each retired memory portion comprising a multiplicity of cells each able to store several selectable values, to program at least some of said multiplicity of cells to a highest value from among said several selectable values as said first duration of time begins.

23. The flash memory apparatus according to claim 1, further arranged to copy, at the beginning of the first duration of time, certain data residing in the retired memory portion to a memory portion out of the certain memory portions;

and copy the certain data from the memory portion out of the certain memory portion to the retired memory portion after the first duration of time expires.

24. A memory device comprising:

an array of semiconductor cells undergoing cycling causing deterioration of said cells; and

at least one heating element operative to heat at least one cell of said array of semiconductor cells without heating at least one other cell of said array of semiconductor cells thereby reducing the cell'"'"'s deterioration due to said cycling.

25. A method for operating a flash memory device comprising a multiplicity of flash memory cells, said method comprising:

programming selected ones from among said multiplicity of cells; and

for at least one individual cell of said multiplicity of cells, tracking the amount of time since programming last occurred in said individual cell.

26. The method according to claim 25, further comprising reserving for data retention purposes, for at least a first duration of time, said first duration being compared against said amount of time, to said at least one individual cell from among said multiplicity of cells including allocating data, during said first duration of time, only to said at least one individual cell, thereby to define at least one of the multiplicity of cells other than said at least one individual cell as a retired cell for said first duration of time.

27. A method for using a flash memory apparatus, the method including:

reserving for data retention purposes, for at least a first duration of time, only certain portions from among said plurality of memory portions including allocating data, during said first duration of time, only to said certain portions, thereby to define at least one of the plurality of memory portions other than said certain portions as a retired memory portion for said first duration of time;

determining to copy data from a certain memory portion of said certain memory portions to a retired memory portion based upon a relationship between an effective cycle count of the certain memory portion and an effective cycle count of the retired memory portion;

wherein an effective cycle count of any memory portion is responsive to a number of erase-write cycles that the memory portion has undergone and to an effective duration of time the memory portion had available to recover from erase-write cycles it has undergone; and

copying the data from the certain memory portion to the retired memory portion.