Semiconductor Device and Wireless Tag Using the Same

• US 20130240877A1
• Filed: 05/01/2013
• Published: 09/19/2013
• Est. Priority Date: 09/19/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Nishijima, Tatsuji
• Granted Patent: US 9,607,975 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: G06K 19/0707 the arrangement being capable of collecting energy from external energy sources, e.g. thermocouples, vibration, electromagnetic radiation G06K19/0702 takes precedence
• CPC Class Codes: G06K 19/0712 the arrangement being capable of triggering distinct operating modes or functions dependent on the strength of an energy or interrogation field in the proximity of the record carrier active means for hindering electromagnetic reading or writing G06K19/07336
• CPC Class Codes: G06K 19/0715 the arrangement including means to regulate power transfer to the integrated circuit
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
• CPC Class Codes: H01L 27/0251 for MOS devices

Abstract

In a wireless tag with which a wireless communication system whose electric power of a carrier wave from a R/W is high, an overvoltage protection circuit is provided to prevent from generating excessive electric power in the wireless tag when the wireless tag receives excessive electric power. However, as noise is generated by operation of the overvoltage protection circuit, an error of reception occurs in receiving a signal whose modulation factor is small. To solve the problem, the maximum value of generated voltage in the wireless tag is held in a memory circuit after the overvoltage protection circuit operates, then the overvoltage protection circuit is controlled in accordance with the maximum value of generated voltage. The voltages at which the overvoltage protection circuit starts and stops operating are different from each other, and hysteresis occurs between the timing when the overvoltage protection circuit starts and stops operating.

Claims

1-5. -5. (canceled)

6. A semiconductor device comprising:

a memory circuit comprising a first transistor and a capacitor; and

a protection circuit electrically connected to the memory circuit,

wherein one of a source and a drain of the first transistor is electrically connected to one electrode of the capacitor,

wherein the other of the source and the drain of the first transistor is electrically connected to the other electrode of the capacitor, and

wherein the first transistor comprises a semiconductor layer including indium, gallium, zinc, and oxygen.

7. The semiconductor device according to claim 6, further comprising a voltage detection circuit electrically connected to the memory circuit.

8. The semiconductor device according to claim 6, further comprising a voltage detection circuit electrically connected to the memory circuit,

wherein the voltage detection circuit is configured to output a potential in accordance with a level of electric power supplied from an external portion;

and

wherein the memory circuit is configured to hold a potential in accordance with a maximum value of the potential output from the voltage detection circuit.

9. The semiconductor device according to claim 6,

wherein the memory circuit includes a reset terminal,

wherein the memory circuit resets a potential which is held when a reset signal is input to the reset terminal, and

wherein the reset terminal is electrically connected to a gate of the first transistor.

10. The semiconductor device according to claim 6, wherein the other electrode of the capacitor is held at a constant potential.

11. A semiconductor device comprising:

a memory circuit comprising a first transistor, a capacitor, and a second transistor; and

a protection circuit electrically connected to the memory circuit, the protection circuit comprising a third transistor,

wherein one of a source and a drain of the first transistor is electrically connected to one electrode of the capacitor,

wherein the other of the source and the drain of the first transistor is electrically connected to the other electrode of the capacitor,

wherein one of a source and a drain of the second transistor is electrically connected to the one of the source and the drain of the first transistor,

wherein a gate of the third transistor is electrically connected to the one electrode of the capacitor, and

wherein each of the first transistor, the second transistor, and the third transistor comprises a semiconductor layer including indium, gallium, zinc, and oxygen.

12. The semiconductor device according to claim 11, further comprising a voltage detection circuit electrically connected to a gate and the other of the source and the drain of the second transistor.

13. The semiconductor device according to claim 11, further comprising a voltage detection circuit electrically connected to a gate and the other of the source and the drain of the second transistor,

wherein the voltage detection circuit is configured to output a potential in accordance with a level of electric power supplied from an external portion;

and

wherein the memory circuit is configured to hold a potential in accordance with a maximum value of the potential output from the voltage detection circuit.

14. The semiconductor device according to claim 11,

wherein the memory circuit includes a reset terminal,

wherein the memory circuit resets a potential which is held when a reset signal is input to the reset terminal, and

wherein the reset terminal is electrically connected to a gate of the first transistor.

15. The semiconductor device according to claim 11, wherein the other electrode of the capacitor is held at a constant potential.