Contact Test Structure and Method

• US 20130240883A1
• Filed: 03/16/2012
• Published: 09/19/2013
• Est. Priority Date: 03/16/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Hsien-Wei, Yu, Tsung-Yuan, Chen, Ying-Ju, Chen, Jie
• Granted Patent: US 9,129,816 B2
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: H01L 22/30 Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03452 Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05541 Structure
• CPC Class Codes: H01L 2224/05555 being circular or elliptic
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05583 Three-layer coating
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06179 : Corner adaptations, i.e. disposition of the bonding areas at the corners of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/06505 : Bonding areas having different materials
• CPC Class Codes: H01L 2224/11015 : for aligning the bump connector, e.g. marks, spacers
• CPC Class Codes: H01L 2224/13006 : Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13022 : the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13026 : relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/14153 : with a staggered arrangement, e.g. depopulated array
• CPC Class Codes: H01L 2224/14155 : Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 23/4824 : Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A system and method for testing electrical connections is provided. In an embodiment one or more floating pads may be manufactured in electrical connection with an underbump metallization structure. A test may then be performed to measure the electrical characteristics of the underbump metallization structure through the floating pad in order to test for defects. Alternatively, a conductive connection may be formed on the underbump metallization and the test may be performed on the conductive connection and the underbump metallization together.

Claims

1. A semiconductor device comprising:

a conductive contact on a substrate, the conductive contact having a first width; and

a first floating test pad adjacent to the conductive contact on the substrate, wherein the first floating test pad is electrically connected to the conductive contact through the substrate, the first floating test pad having a second width that is different than the first width.

2. The semiconductor device of claim 1, further comprising a second floating test pad on the substrate, wherein the second floating test pad is electrically connected to the conductive contact and the first floating test pad through the substrate, the second floating test pad having a third width that is different than the first width.

3. The semiconductor device of claim 2, wherein the first floating test pad, the second floating test pad, and the conductive contact are aligned in a first direction.

4. The semiconductor device of claim 2, wherein the first floating test pad and the conductive contact are aligned along a first direction, and the second floating test pad and the conductive contact are aligned along a second direction different from the first direction.

5. The semiconductor device of claim 4, wherein the conductive contact is located at a corner of the substrate.

6. The semiconductor device of claim 1, wherein the conductive contact comprises a first material and the first floating test pad comprises the first material.

7. The semiconductor device of claim 1, further comprising a conductive bump on the conductive contact.

8. The semiconductor device of claim 1, further comprising a post passivation interconnect electrically connecting the first floating pad to the conductive contact through the substrate.

9. A semiconductor device comprising:

a first conductive contact on a substrate;

a second conductive contact on the substrate, the second conductive contact being located a first distance from the first conductive contact; and

a first test pad located a second distance from the first conductive contact, the first distance being less than the second distance, the first test pad being smaller than the first conductive contact; and

an interconnect within the substrate, the interconnect electrically connecting the first test pad to the first conductive contact.

10. The semiconductor device of claim 9, further comprising a second test pad on the substrate located a third distance from the first conductive contact, the third distance being less than the first distance, wherein the interconnect electrically connects the second test pad to the first conductive contact.

11. The semiconductor device of claim 10, wherein the first test pad, the second test pad, and the first conductive contact are aligned in a first direction.

12. The semiconductor device of claim 10, wherein the first test pad and the first conductive contact are aligned in a first direction, and the second test pad and the first conductive contact are aligned in a second direction perpendicular to the first direction.

13. The semiconductor device of claim 10, wherein the first test pad is offset from a line between the first conductive contact and the second conductive contact.

14. The semiconductor device of claim 9, further comprising a conductive bump on the first conductive contact.

15. A method of manufacturing a semiconductor device, the method comprising:

forming an interconnect on a substrate;

forming a passivation layer over the interconnect;

forming a first opening and a second opening through the passivation layer to expose a first portion of the interconnect and a second portion of the interconnect;

forming a conductive contact in the first opening in contact with the interconnect; and

forming a first test pad in the second opening in contact with the interconnect, the first test pad having a smaller lateral dimension than the conductive contact.

16. The method of claim 15, wherein the forming the conductive contact and the forming the first test pad are performed simultaneously.

17. The method of claim 15, further comprising forming a conductive bump on the conductive contact.

18. The method of claim 15, further comprising testing the conductive contact using the first test pad.

19. The method of claim 15, further comprising:

forming a third opening through the passivation layer to expose a third portion of the interconnect; and

forming a second test pad in the third opening in contact with the interconnect.

20. The method of claim 19, wherein the first test pad and the conductive contact are aligned in a first direction and wherein the second test pad and the conductive contact are aligned in a second direction perpendicular with the first direction.