SEMICONDUCTOR ELEMENT HAVING HIGH BREAKDOWN VOLTAGE

• US 20130240895A1
• Filed: 08/09/2012
• Published: 09/19/2013
• Est. Priority Date: 03/16/2012
• Status: Active Grant

• Current Assignee: National Central University
• Original Assignee: CHYI Jen-Inn
• Inventors: CHYI, Jen-Inn, Lee, Geng-Yen, Liu, Hsueh-Hsing
• Granted Patent: US 8,586,995 B2
• Time in Patent Office: Days
• US Class Current: 257/76
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/475 on AIII-BV compounds
• CPC Class Codes: H01L 29/66212 Schottky diodes
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A semiconductor element having a high breakdown voltage includes a substrate, a buffer layer, a semiconductor composite layer and a bias electrode. The buffer layer disposed on the substrate includes a high edge dislocation defect density area. The semiconductor composite layer disposed on the buffer layer includes a second high edge dislocation defect density area formed due to the first high edge dislocation defect density area. The bias electrode is disposed on the semiconductor composite layer. A virtual gate effect of defect energy level capturing electrons is generated due to the first and second high edge dislocation defect density areas, such that an extended depletion region expanded from the bias electrode is formed at the semiconductor composite layer. When the bias electrode receives a reverse bias, the extended depletion region reduces a leakage current and increases the breakdown voltage of the semiconductor element.

Claims

1. A semiconductor element having a high breakdown voltage, comprising:

a substrate;

a buffer layer, disposed on the substrate, comprising a first high edge dislocation defect density area;

a semiconductor composite layer, disposed on the buffer layer, comprising a second high edge dislocation defect density area formed due to the first high edge dislocation defect density area; and

a bias electrode, disposed on the semiconductor composite layer;

wherein, the first and second high edge dislocation defect density areas generating a virtual gate effect of defect energy level capturing electrons to form an extended depletion region expanded from the bias electrode at the semiconductor composite layer.

2. The semiconductor element of claim 1, wherein the semiconductor composite layer comprises a barrier layer located away from the buffer layer, and a channel layer located adjacent to the barrier layer and between the barrier layer and the buffer layer, and the barrier layer has an energy level greater than that of the channel layer.

3. The semiconductor element of claim 2, wherein the channel layer is formed from a material selected from the group consisting of GaN, AlGaN and InAlGaN.

4. The semiconductor element of claim 2, wherein a full-width at half-maximum (FWHM) value of an X-ray rocking curve (XRC) at a (0002) plane of the second high edge dislocation defect density area is smaller than 250 arc seconds, and the FWHM value of the XRC at a (1-102) plane of the second high edge dislocation defect density area is between 500 and 2500 arc seconds.

5. The semiconductor element of claim 2, wherein the barrier layer is formed from a material selected from the group consisting of AlGaN, AlInN and AlGaInN.

6. The semiconductor element of claim 1, wherein the buffer layer is formed from a material of AlN.

7. The semiconductor element of claim 1, wherein an FWHM value of an XRC at a (0002) plane of the first high edge dislocation defect density area is smaller than 150 arc seconds, and the FWHM value of the XRC at a (1-102) plane of the first high edge dislocation defect density area is between 1000 and 5000 arc seconds.

8. The semiconductor element of claim 1, wherein a temperature for developing the buffer layer is between 1100°

C. and 1200°

C.

9. The semiconductor element of claim 1, further comprising an intermediate layer disposed between the buffer layer and the semiconductor composite layer.

10. The semiconductor element of claim 9, wherein the intermediate layer is formed from a material selected from the group consisting of GaN, AlGaN and AlInN.

11. The semiconductor element of claim 1, further comprising a cladding layer disposed between the bias electrode and the semiconductor composite layer.

12. The semiconductor element of claim 11, wherein the cladding layer is formed from a material of GaN or GaInN.