TRANSISTOR ARRAY WITH A MOSFET AND MANUFACTURING METHOD

• US 20130240981A1
• Filed: 04/22/2013
• Published: 09/19/2013
• Est. Priority Date: 04/22/2011
• Status: Active Application

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: SCHULZE, Hans-Joachim, HUTZLER, Michael, SIEMIENIEC, Ralf
• Application Number:
  US13/867,215
• Publication Number:
  US 20130240981A1
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722

Abstract

Disclosed are a semiconductor device and a method for producing a semiconductor device. A MOSFET may have a source region, a drift region and a drain region of a first conductivity type, a body region of a second conductivity type disposed between the source region and the drift region, and a gate electrode disposed adjacent to said body region. The gate electrode may be isolated from the body region by a dielectric, and have a source electrode contacting the source region and the body region. A self-locking JFET, associated with the MOSFET, may have a channel region of the first conductivity type, the channel region connected between the source electrode and the drift region, and coupled to and adjacent the body region.

Claims

16. A MOSFET, comprising:

a semiconductor body having a source region, a drift region and a drain region having a first conductivity type and a body region having a second conductivity type, the body region being between the source region and the drift region;

a gate electrode disposed adjacent the body region, the gate electrode being isolated by a gate dielectric;

a source electrode which contacts the source region and the body region; and

a channel region of the first conductivity type extending from the source electrode to the drift region, so that a pn junction between the body region and the channel region is provided, wherein a doping concentration of the body region and a width of the channel region are such that the intrinsic depletion zone of the channel region cuts off when the MOSFET is in a non-biased state.

17. The MOSFET of claim 16, further comprising:

a depletion control region of the second conductivity type, wherein the depletion control region has a higher doping concentration than the body region, is electrically connected to the source electrode and is adjacent to the channel region.

18. The MOSFET according to claim 16, wherein the JFET has a current flow direction, and wherein the channel region has a width (d) in a direction perpendicular to the current flow direction, wherein the width (d) is between 0.1 μ

m and 0.8 μ

m.

19. The MOSFET according to claim 18, wherein the body region surrounds the channel region perpendicular to the current flow direction in one direction.

21. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor body having a drift region of a first conductivity type, a body region having a second conductivity type that is complementary to the first conductivity type, the body region being adjacent to the drift region, a source region having the first conductivity type and adjacent to the body region, and a gate electrode adjacent to the body region, the gate electrode isolated from the body region by a gate dielectric;

forming a channel region in the body region and spaced from the gate dielectric, wherein the channel region extends up from the drift region to the source region;

producing at least one trench in the source region, the body region and the channel region, a first sidewall of the trench adjacent to the body region and a second sidewall of the trench, opposite of the first sidewall, adjacent to the channel region;

forming a depletion control region having the second conductivity type, the depletion control region being adjacent to the trench, at least in the channel region and spaced from the source region; and

forming a source electrode in the trench.

1. A semiconductor device, comprising:

a MOSFET having a source region, a drift region and a drain region of a first conductivity type, a body region of a second conductivity type disposed between the source region and the drift region, and a gate electrode disposed adjacent to said body region, the gate electrode being isolated from the body region by a dielectric, and having a source electrode contacting the source region and the body region; and

a self-locking JFET with a channel region of the first conductivity type, the channel region connected between the source electrode and the drift region, and coupled to and adjacent the body region.

2. The semiconductor device according to claim 1, further comprising:

a depletion control region of the second conductivity type,

wherein the depletion control region has a higher doping concentration than the body region, is electrically connected to the source electrode, and is adjacent to the channel region.

3. The semiconductor device according to claim 2, further comprising:

a semiconductor body having a first surface,

wherein the depletion control region is arranged spaced from the first surface.

4. The semiconductor device according to claim 3, wherein a distance between the first surface and depletion control region is between 0.1 μ

m and 3 μ

m.

5. The semiconductor device according to claim 3, wherein a portion of the source electrode is arranged in a trench, the trench starting from the first surface and extends to the depletion control region.

6. The semiconductor device according to claim 5, wherein the trench separates the channel region from the body region.

7. The semiconductor device according to claim 1, wherein the channel region is at least partially on the body region and the channel region forms a pn junction with said body region.

8. The semiconductor device according to claim 1, further comprising:

a semiconductor body, said source region and the drain region in a vertical direction of the semiconductor body being spaced apart from one another.

9. The semiconductor device according to claim 8, wherein said channel region is positioned in a vertical direction of the semiconductor body along said body region.

10. The semiconductor device according to claim 1, wherein a doping concentration of the channel region corresponds to a doping concentration of the drift region.

11. The semiconductor device according claim 1, wherein the channel region adjoins to the drift region.

12. The semiconductor device according to claim 1, wherein the JFET has a current flow direction and the channel region has a width (d) in a direction perpendicular to the current flow direction, wherein the width (d) is between 0.1 μ

m and 0.8 μ

m.

13. The semiconductor device according to claim 1, wherein said JFETs has a current flow direction, the channel region and the body region being perpendicular to the current flow direction.

14. The semiconductor device according to claim 1, further comprising:

an insulating layer extending to the channel region on a side opposite to the body region adjoined to the channel region.

15. The semiconductor device according to claim 1, wherein JFET has a current flow direction and the channel region has a width (d) in a direction perpendicular to the direction of current flow;

an intrinsic depletion region of the pn junction between the body region and the channel region is present, when the MOSFET is in a non-biased state,

a width of the depletion region depends on an intrinsic doping concentration of the channel region, and

the doping concentration of the channel region is selected so that a width of the intrinsic depletion region is larger than the width of the channel region.

20. The MOSFET according to claim 15, further comprising:

an insulating layer disposed adjacent to the channel region on an opposite side to the body region.

24. The method according to claim 21, wherein the gate electrode is disposed in a second trench which extends from a first side of the semiconductor body, through the source region and the body region, and into the drift region.

25. The method according to claim 21, wherein the semiconductor body has two gate electrodes or two gate electrode portions which are arranged in a horizontal direction, spaced from each other, wherein the channel region and the body region are disposed between the two gate electrodes or gate electrode portions.

24-1. The method according to claim 21, wherein forming the channel region comprises utilizing an implantation and/or diffusion process.

25-2. The method according to claim 21, wherein the producing of the at least one trench comprises using an etch mask, the etch mask remaining after forming the at least one trench.

26. The method according to claim 26, further comprising:

forming a drain region of the first conductivity type, the drain region at least spaced apart from the body region.