PROCESS FOR FABRICATING A FIELD-EFFECT TRANSISTOR DEVICE IMPLEMENTED ON A NETWORK OF VERTICAL NANOWIRES, THE RESULTING TRANSISTOR DEVICE, AN ELECTRONIC DEVICE COMPRISING SUCH TRANSISTOR DEVICES AND A PROCESSOR COMPRISING AT LEAST ONE SUCH DEVICE

• US 20130240983A1
• Filed: 11/24/2011
• Published: 09/19/2013
• Est. Priority Date: 11/26/2010
• Status: Active Grant

• Current Assignee: Centre National De La Recherche Scientifique
• Original Assignee: Centre National De La Recherche Scientifique
• Inventors: Larrieu, Guilhem
• Granted Patent: US 9,379,238 B2
• Time in Patent Office: Days
• US Class Current: 257/329
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: C01B 32/15 Nano-sized carbon materials
• CPC Class Codes: H01L 21/02606 Nanotubes carbon nanotubes H10K85/211
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/413 Nanosized electrodes, e.g. nanowire electrodes comprising one or a plurality of nanowires nanosized carbon materials, e.g. carbon nanotubes, per se C01B32/15; transparent electrodes comprising carbon nano-tubes H10K30/821, nanotechnology per se B82B
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: Y10S 977/762 Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
• CPC Class Codes: Y10S 977/938 Field effect transistors, FETS, with nanowire- or nanotube-channel region

Abstract

A process for fabricating a field-effect transistor device (20) implemented on a network of vertical nanowires (24), includes: producing a source electrode (26) and a drain electrode (30) at each end of each nanowire (24) symmetrically relative to the gate electrode of each elementary transistor implemented on a nanowire; creating a gate electrode by depositing a layer (38) of conductive material around a layer (36) of dielectric material that surrounds a portion of each nanowire (24), a single conductive layer (38) being used for all of the nanowires and the thickness of the conductive layer corresponding to the gate length of the transistor device; and insulating each electrode with a planar layer (32, 34) of a dielectric material in order to form a nanoscale gate and in order to insulate the contacts of each elementary transistor between the gate and the source and the gate and the drain.

Claims

1-15. -15. (canceled)

16. A fabrication process for fabricating a field-effect transistor device implemented on a network of vertical nanowires, including a plurality of elementary transistors, each elementary transistor comprising a source electrode and a drain electrode each positioned at one end of a vertical nanowire of the network and connected by a channel and each elementary transistor including a gate electrode surrounding each vertical nanowire of the network, the drain, source and gate electrodes of the elementary transistors implemented on the nanowires are respectively connected to each other so as to form unique drain, source and gate electrodes of the transistor device,

wherein it comprises the following steps:

producing source and drain electrodes at each end of each vertical nanowire, the source and drain electrodes being positioned symmetrically with respect to the gate electrode of each elementary transistor implemented on a nanowire;

creating a gate electrode by depositing a layer of dielectric material surrounding a portion of each nanowire and depositing a layer of conductive material around each layer of dielectric material surrounding the portion of each nanowire, the layer of conductive material being unique for all of the nanowires of the network and the thickness of the layer of conductive material corresponding to the length of the gate of the transistor device; and

insulating each electrode using a planar layer of a dielectric material so as to form a nanoscale gate and insulate the contacts between the source and the gate and between the drain and the gate of each elementary transistor implemented on a nanowire.

17. The fabrication process according to claim 16, wherein the source and drain electrodes are positioned symmetrically with respect to the gate electrode using an auto-alignment process of the source and drain electrodes on the gate electrode of each transistor implemented around a nanowire.

18. The fabrication process according to claim 16, wherein the step for insulating each source and drain electrode using the dielectric is done by depositing a first layer of dielectric material and a second layer of dielectric material, the layer of conductive material creating the gate electrode being deposited above the first layer of dielectric material and the second layer of dielectric material being deposited above the layer of conductive material creating the gate electrode, the thickness of the first and second layers of dielectric material and the position of the layer of conductive material creating the gate electrode being predefined so that the source and drain electrodes are positioned symmetrically with respect to the gate electrode of each transistor implemented on a nanowire.

19. The fabrication process according to claim 18, wherein the flatness of the first layer of dielectric material is defined with a precision substantially less than or equal to 5 nm.

20. The fabrication process according to claim 18, wherein the dielectric material of the first and second layers of dielectric material is a fluent inorganic resin.

21. The fabrication process according to claim 16, wherein the thickness of the layer of conductive material creating the gate electrode is smaller than 20 nm, the thickness of the layer defining the length of the gate.

22. A field-effect transistor device implemented on a network of vertical nanowires including a plurality of elementary transistors, each elementary transistor comprising a source electrode and a drain electrode each positioned at one end of a vertical nanowire of the network and connected by a channel and each elementary transistor including a gate electrode surrounding each vertical nanowire of the network, the drain, source and gate electrodes of the elementary transistors implemented on the nanowires are respectively connected to each other so as to form unique drain, source and gate electrodes of the transistor device, wherein:

the source and drain electrodes are positioned symmetrically with respect to the gate electrode of each transistor implemented on a nanowire;

the gate electrode of a transistor is formed by a layer of dielectric material surrounding a portion of each nanowire and a layer of conductive material around each layer of dielectric material surrounding the portion of each nanowire, the layer of conductive material being unique for all of the nanowires of the network and the thickness of the layer of conductive material corresponds to the length of the gate of the transistor device; and

the device includes a dielectric material so as to insulate each source and drain electrode to form the contacts between the source and gate and between the drain and gate of each transistor implemented on a nanowire.

23. The transistor device according to claim 22, wherein the gate length of the transistor is less than 20 nm.

24. The transistor device of a material according to claim 22, wherein the nanowires are made of a material from group IV or groups III-V according to the periodic table of elements.

25. The transistor device according to of claim 22, wherein the nanowires are made from silicon.

26. The transistor device according to claim 22, wherein the conductive material creating the gate electrode is made from metal, silicide, silicon or polysilicon.

27. The transistor device according to of claim 22, wherein the dielectric material surrounding a portion of each nanowire is made from silicon dioxide SiO₂ or an insulating material having a high dielectric coefficient among aluminum-, zirconium-, hafnium-, gadolinium-, or lanthanum-based oxides.

28. An electronic device wherein it comprises at least one device with a plurality of field-effect transistors implemented on a network of vertical nanowires according to claim 22.

29. The electronic device according to claim 28, wherein it belongs to the group consisting of:

a CMOS inverter, a logic circuit, a multiplexer, a volatile memory, a non-volatile memory, and a device for detecting gas or biochemical agents.

30. A processor, wherein it includes at least one electronic device according to claim 28.