NOVEL SEMICONDUCTOR DEVICE AND STRUCTURE

• US 20130241026A1
• Filed: 03/17/2012
• Published: 09/19/2013
• Est. Priority Date: 03/17/2012
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak C., Cronquist, Brian
• Granted Patent: US 9,000,557 B2
• Time in Patent Office: Days
• US Class Current: 257/506
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A device including a first layer of first transistors interconnected by at least one first interconnection layer, wherein the first interconnection layer includes copper or aluminum, a second layer including second transistors, the second layer overlaying the first interconnection layer, wherein the second layer is less than 2 micron thick, wherein the second layer has a coefficient of thermal expansion; and a connection path connecting at least one of the second transistors to the first interconnection layer, wherein the connection path includes at least one through-layer via, and wherein the through-layer via includes material whose co-efficient of thermal expansion is within 50 percent of the second layer coefficient of thermal expansion.

Claims

1. A device comprising:

a first layer of first transistors interconnected by at least one first interconnection layer, wherein said first interconnection layer comprises copper or aluminum;

a second layer comprising second transistors, said second layer overlaying said first interconnection layer, wherein said second layer is less than 2 micron thick, wherein said second layer has a coefficient of thermal expansion; and

a connection path connecting at least one of said second transistors to said first interconnection layer,

wherein said connection path comprises at least one through-layer via, and

wherein said through-layer via comprises material whose co-efficient of thermal expansion is within 50 percent of said second layer coefficient of thermal expansion.

2. A device according to claim 1 wherein said through-layer via comprises tungsten.

3. A device according to claim 1 wherein said connection path comprises mostly copper or aluminum.

4. A device according to claim 1 wherein said second layer further comprises a region of high quality oxide isolation, wherein said high quality oxide isolation is comparable to one produced by using radical oxidation or a high density plasma deposition.

5. A device according to claim 1 wherein said first layer comprises at least one first alignment mark, and wherein at least one said through-layer via is aligned at least partially to said first alignment mark with less than 10 nm alignment error.

6. A device comprising:

a first layer of first transistors interconnected by at least one first interconnection layer, wherein said first interconnection layer comprises copper or aluminum;

a second layer comprising second transistors, said second layer overlaying said first interconnection layer, wherein said second layer is less than 2 micron thick; and

a connection path connecting at least one of said second transistors to said first interconnection layer,

wherein said connection path comprises at least one through-layer via,

wherein said second layer further comprises a region of high quality oxide isolation,

wherein said high quality oxide isolation is comparable to one produced by using radical oxidation or a high density plasma deposition.

7. A device according to claim 6 wherein said through-layer via comprises tungsten.

8. A device according to claim 6 wherein said connection path comprises mostly copper or aluminum.

9. A device according to claim 6 wherein said through-layer via comprises material whose co-efficient of thermal expansion is within 50 percent of a coefficient of thermal expansion of said second layer.

10. A device according to claim 6 wherein said first layer comprises at least one first alignment mark, and wherein at least one said through-layer via is aligned at least partially to said first alignment mark with less than 10 nm alignment error.

11. A device comprising:

a first layer of first transistors interconnected by at least one first interconnection layer, wherein said first interconnection layer comprises copper or aluminum;

a second layer comprising second transistors, said second layer overlaying said first interconnection layer, wherein said second layer is less than 2 micron thick; and

a connection path connecting at least one of said second transistors to said first interconnection layer,

wherein said connection path comprises at least one through-layer via,

wherein said at least one through-layer via is forming a direct contact with said at least one of said second transistors.

12. A device according to claim 11 wherein said second transistors are aligned with said first transistors.

13. A device according to claim 11 wherein said connection path comprises mostly copper or aluminum.

14. A device according to claim 11 wherein said second layer further comprises a region of high quality oxide isolation, wherein said high quality oxide isolation is comparable to one produced by using radical oxidation or a high density plasma deposition.

15. A device according to claim 11 wherein said through-layer via comprises material whose co-efficient of thermal expansion is within 50 percent of a coefficient of thermal expansion of said second layer.

16. A device comprising:

a first layer of first transistors interconnected by at least one first interconnection layer, wherein said first interconnection layer comprises copper or aluminum;

a second layer comprising second transistors, said second layer overlaying said first interconnection layer, wherein said second layer is less than 2 micron thick; and

a connection path connecting at least one of said second transistors to said first interconnection layer,

wherein said connection path comprises at least one through-layer via, and

wherein said through-layer via comprises tungsten.

17. A device according to claim 16 wherein said connection path comprises mostly copper or aluminum.

18. A device according to claim 16 wherein said second layer further comprises a region of high quality oxide isolation, wherein said high quality oxide isolation is comparable to one produced by using radical oxidation or a high density plasma deposition.

19. A device according to claim 16 wherein said first layer comprises at least one first alignment mark, and wherein at least one said through-layer via is aligned at least partially to said first alignment mark with less than 10 nm alignment error.

20. A device according to claim 16 wherein said at least one of through-layer via is forming a direct contact with at least one of said second transistors.