NOVEL SEMICONDUCTOR DEVICE AND STRUCTURE
First Claim
1. A device comprising:
- a first layer of first transistors interconnected by at least one first interconnection layer, wherein said first interconnection layer comprises copper or aluminum;
a second layer comprising second transistors, said second layer overlaying said first interconnection layer, wherein said second layer is less than 2 micron thick, wherein said second layer has a coefficient of thermal expansion; and
a connection path connecting at least one of said second transistors to said first interconnection layer,wherein said connection path comprises at least one through-layer via, andwherein said through-layer via comprises material whose co-efficient of thermal expansion is within 50 percent of said second layer coefficient of thermal expansion.
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Accused Products
Abstract
A device including a first layer of first transistors interconnected by at least one first interconnection layer, wherein the first interconnection layer includes copper or aluminum, a second layer including second transistors, the second layer overlaying the first interconnection layer, wherein the second layer is less than 2 micron thick, wherein the second layer has a coefficient of thermal expansion; and a connection path connecting at least one of the second transistors to the first interconnection layer, wherein the connection path includes at least one through-layer via, and wherein the through-layer via includes material whose co-efficient of thermal expansion is within 50 percent of the second layer coefficient of thermal expansion.
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Citations
20 Claims
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1. A device comprising:
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a first layer of first transistors interconnected by at least one first interconnection layer, wherein said first interconnection layer comprises copper or aluminum; a second layer comprising second transistors, said second layer overlaying said first interconnection layer, wherein said second layer is less than 2 micron thick, wherein said second layer has a coefficient of thermal expansion; and a connection path connecting at least one of said second transistors to said first interconnection layer, wherein said connection path comprises at least one through-layer via, and wherein said through-layer via comprises material whose co-efficient of thermal expansion is within 50 percent of said second layer coefficient of thermal expansion. - View Dependent Claims (2, 3, 4, 5)
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6. A device comprising:
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a first layer of first transistors interconnected by at least one first interconnection layer, wherein said first interconnection layer comprises copper or aluminum; a second layer comprising second transistors, said second layer overlaying said first interconnection layer, wherein said second layer is less than 2 micron thick; and a connection path connecting at least one of said second transistors to said first interconnection layer, wherein said connection path comprises at least one through-layer via, wherein said second layer further comprises a region of high quality oxide isolation, wherein said high quality oxide isolation is comparable to one produced by using radical oxidation or a high density plasma deposition. - View Dependent Claims (7, 8, 9, 10)
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11. A device comprising:
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a first layer of first transistors interconnected by at least one first interconnection layer, wherein said first interconnection layer comprises copper or aluminum; a second layer comprising second transistors, said second layer overlaying said first interconnection layer, wherein said second layer is less than 2 micron thick; and a connection path connecting at least one of said second transistors to said first interconnection layer, wherein said connection path comprises at least one through-layer via, wherein said at least one through-layer via is forming a direct contact with said at least one of said second transistors. - View Dependent Claims (12, 13, 14, 15)
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16. A device comprising:
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a first layer of first transistors interconnected by at least one first interconnection layer, wherein said first interconnection layer comprises copper or aluminum; a second layer comprising second transistors, said second layer overlaying said first interconnection layer, wherein said second layer is less than 2 micron thick; and a connection path connecting at least one of said second transistors to said first interconnection layer, wherein said connection path comprises at least one through-layer via, and wherein said through-layer via comprises tungsten. - View Dependent Claims (17, 18, 19, 20)
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Specification