System and Apparatus for Driver Circuit for Protection of Gates of GaN FETs

• US 20130241621A1
• Filed: 03/16/2012
• Published: 09/19/2013
• Est. Priority Date: 03/16/2012
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Huertas-Sanchez, Luis A., Forghani-Zadeh, Hassan Pooya
• Granted Patent: US 8,593,211 B2
• Time in Patent Office: Days
• US Class Current: 327/315
• CPC Class Codes: H03K 17/08122 in field-effect transistor switches

Abstract

A half-bridge power circuit comprises a first gallium nitride field effect transistor (GaN FET); a first driver coupled to a gate of the first GaN FET; an anode of a capacitor coupled to an output of the driver and a source of the first GaN FET; a diode having a cathode coupled to the cathode of the capacitor; and a bootstrap capacitor clamp (BCC) controller, including: a field effect transistor (FET) coupled to an anode of the diode, and a comparator coupled to a gate of the FET, the comparator configured to receive as inputs: a) a signal representative of an input voltage (VDRV) applied to the FET; b) a ground; c) a boot signal representative of a voltage at the anode of the capacitor (Boot); and d) a signal representative of a voltage at the source of the first GaN FET (SW).

Claims

1. An apparatus, comprising:

a first gallium nitride field effect transistor (GaN FET);

a first driver coupled to a gate of the first GaN FET;

an anode of a capacitor coupled to an output of a driver and a source of the first GaN FET;

a diode having a cathode coupled to the cathode of the capacitor; and

a bootstrap capacitor clamp (BCC) controller, including;

a field effect transistor (FET) coupled to an anode of the diode; and

a comparator coupled to a gate of the FET, the comparator configured to receive as inputs;

a) a signal representative of an input voltage (VDRV) applied to the FET;

b) a ground;

c) a boot signal representative of a voltage at the anode of the capacitor (Boot); and

d) a signal representative of a Voltage at the source of the first GaN FET,

wherein the BCC controller is configured to compare;

a) a difference of;

i) the VDRV and the GND, to generate a first comparison signal, to

b) a difference of ii) the Boot and the source of the GaN FET, to generate a second comparison signal;

wherein the BCC controller is further configured to maintain a relationship between the first comparison signal and the second comparison signal base on the comparison, and

wherein the BCC controller is further configured to drive a gate output signal to the first GaN FET to maintain this relationship.

2. The apparatus of claim 1, wherein the drain of the FET is coupled to the anode of the diode.

3. The apparatus of claim 1, wherein the GaN FET, further comprising a drain of a second GaN FET coupled to a source of the first GaN FET, and the first GaN FET is a high side GaN FET, and the second GaN FET is a low side GaN FET.

4. The apparatus of claim 3, wherein an inductor is coupled to the source of the first GaN FET.

5. The apparatus of claim 4, wherein said apparatus includes a half bridge voltage rectifier.

6. The apparatus of claim 1, wherein the relationship is a substantially equal voltage drop comparison between:

i) the VDRV and the GND, and ii) ii) the Boot and the source of the GaN FET.

7. The apparatus of claim 1, wherein the driver is a first driver, and a deadtime control is coupled to an input of the first driver and a second driver, wherein the second driver is also coupled to a gate of a second GaN FET, the second GaN FET coupled to the source of the first GaN FET.

8. The apparatus of claim 1, further comprising an upper driver rail of the first driver coupled to a cathode of the capacitor;

and a lower rail of the first driver coupled to the source of the GaN FET.

9. A system, comprising:

a) a GaN FET;

b) a bootstrap capacitor clamp (BCC) controller coupled to a gate of the GaN FET, the BCC controller comprising;

a comparator;

a FET, a gate of which is coupled to an output of the comparator;

a first isolation switch coupled to a positive input of the comparator, a drain of the first isolation switch coupled between a first resistor and a second resistor, wherein the first resistor is also coupled to an anode of a capacitor, and wherein the second resistor is coupled to a ground;

a second isolation switch coupled to a negative input of the comparator, a drain of the second isolation switch coupled between a third resistor and a fourth resistor, wherein the third resistor is also coupled to a signal representative of a signal voltage (VDRV) and wherein the fourth resistor is also coupled to a source of the GaN FET.

10. The system of claim 9, wherein the first isolation switch and the second isolation switch are enabled when receiving a low side GaN FET on (LS_ON) signal.

11. The system of claim 10, wherein the comparator turns on the FET when a difference between the Boot and GND voltage is greater than that of a difference between a VDRV and SW voltage.

12. The system of claim 9, further comprising a diode coupled between the BCC controller and a gate of the GaN FET.

13. The system of claim 12, further comprising the capacitor coupled between the diode and a source of the GaN FET.

14. The system of claim 9, wherein driving the FET off by the comparator allows a voltage across the boot capacitor to float, thereby not overdriving a difference between a gate and a source of the GaN FET.

15. The system of claim 9, wherein the BCC controller is configured to keep a voltage difference between a first input voltage of the amplifier and a second input of an amplifier substantially constant.

16. The system of claim 11, wherein said system is embodied upon an integrated circuit.

17. A system, comprising:

a first gallium nitride field effect transistor (GaN FET);

a first driver coupled to a gate of the first GaN FET;

an anode of a capacitor coupled to an output of a driver and a source of the GaN FET;

a diode having a cathode coupled to the cathode of the capacitor; and

a bootstrap capacitor clamp (BCC) controller, including;

a field effect transistor (FET) coupled to an anode of the diode; and

a comparator coupled to a gate of the FET, the comparator configured to receive as inputs;

a) a signal representative of an input voltage (VDRV) applied to the source of the FET;

b) a ground;

c) a boot signal representative of a voltage at the anode of the capacitor; and

d) a signal representative of a voltage at the source of the first GaN FET, wherein the bootstrap capacitor clamp is configured to compare;

a) a difference of ;

i) the VDRV and the GND to generate a first comparison signal;

to

b) a difference of ii) the Boot and the SW to generate a second comparison signal;

wherein the BCC controller is configured to maintain a relationship

between the first comparison signal and the second comparison signal base on the comparison, and

wherein the BCC controller is further configured to drive a gate output signal to the a drain of a second GaN FET coupled to a source of the first GaN FET;

an inductor coupled to a source of the first GaN FET; and

a drain of a second GaN FET coupled to a source of the first GaN FET.

18. The system of claim 17, wherein the BCC controller further comprises:

a FET, a gate of which is coupled to an output of the comparator;

a first isolation switch coupled to a positive input of the comparator, a drain of the first isolation switch coupled between a first resistor and a second resistor, wherein the first resistor is also coupled to an anode of the capacitor, and wherein the second resistor is coupled to a ground;

a second isolation switch coupled to a negative input of the comparator, a drain of the second isolation switch coupled between a third resistor and a fourth resistor, wherein the third resistor is also coupled to a signal representative of a signal voltage (VDRV) and wherein the fourth resistor is also coupled to a source of the GaN FET.

19. The system of claim 18, wherein driving the FET off by the comparator allows a voltage across the boot capacitor to float, thereby not overdriving a difference between a gate and a source of the GaN FET.

20. The system of claim 18, wherein the BCC controller is configured to keep a voltage difference between a first input voltage of the amplifier and a second input of an amplifier substantially constant.

21. The system of claim 18, wherein said apparatus includes a half bridge voltage rectifier.

22. The system of claim 18, wherein the first GaN FET is a high side GaN FET, and the second GaN FET is a low side FET.

23. The system of claim 23, wherein said system is embodied upon an integrated circuit.