Linearization Circuit and Related Techniques

• US 20130241655A1
• Filed: 03/07/2013
• Published: 09/19/2013
• Est. Priority Date: 03/19/2012
• Status: Active Grant

• Current Assignee: Auriga Measurement Systems
• Original Assignee: Auriga Measurement Systems
• Inventors: Liss, Cheryl V., Tajima, Yusuke, Shen-Schultz, Qin, Muir, John
• Granted Patent: US 9,030,255 B2
• Time in Patent Office: Days
• US Class Current: 330/285
• CPC Class Codes: H03F 1/0288 using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
• CPC Class Codes: H03F 1/3247 using feedback acting on predistortion circuits H03F1/3264 takes precedence
• CPC Class Codes: H03F 2201/3221 Predistortion by overamplifying in a feedforward stage the distortion signal to have a combined main signal and "negative" distortion to form the predistorted signal for a further stage. so that after amplification in the further stage only the amplified main signal remains
• CPC Class Codes: H03F 3/68 Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602
• CPC Class Codes: H03G 3/00 Gain control in amplifiers or frequency changers

Abstract

Circuits and techniques to linearize the operation of an RF power amplifier are described. A linearizer circuit may include a non-amplification signal path which includes a delay line and an amplification signal path which includes at least one amplifier stage. In some embodiments, the amplification signal path may include an odd number of amplification stages. The linearizer may be used to precondition an input signal of an RF power amplifier in a manner that improves the overall linearity of operation.

Claims

1. A linearizer circuit comprising:

a divider circuit having an input and first and second outputs;

a first radio frequency (RF) signal path having an input and an output, the input being coupled to the first output of the divider circuit, the first RF signal path comprising a delay line having a predetermined length;

a second RF signal path having an input and an output, the input being coupled to the second output of the divider circuit, the second RF signal path comprising a transistor amplifier consisting of an odd number of gain stages; and

a combiner circuit having a first input, a second input, and an output, the first input of the combiner circuit being coupled to the output of the first RF signal path and the second input of the combiner circuit being coupled to the output of the second RF signal path.

2. The linearizer circuit of claim 1 wherein:

the divider circuit is configured to create a nominal 90 degree phase difference between output signals at the first and second outputs thereof; and

the combiner circuit is adapted to receive two substantially opposite phase signals at the first and second inputs thereof with an additional nominal 90 degree phase shift and combine the signals while cancelling the 90 degree phase shift.

3. The linearizer circuit of claim 1 wherein the second RF signal path further comprises:

a first variable attenuator coupled between the input of the second RF signal path and an input of the transistor amplifier; and

a second variable attenuator coupled between an output of the transistor amplifier and the output of the second RF signal path.

4. The linearlizer circuit of claim 3, further comprising:

circuitry for adjusting a bias level applied to the transistor amplifier; and

circuitry for adjusting an attenuation level of at least one of the first and second variable attenuators.

5. The linearizer circuit of claim 4, wherein:

the circuitry for adjusting an attenuation level comprises circuitry for adjusting the attenuation level in conjunction with a change in bias voltage level applied to the transistor amplifier.

6. The linearizer circuit of claim 3, wherein:

the circuitry for adjusting a bias level and the circuitry for adjusting an attenuation level are configured to adjust an output amplitude of the second RF signal path so that it is substantially equal to an output amplitude of the first RF signal path when an input power level of the linearizer circuit is below a threshold value.

7. The linearizer circuit of claim 3, wherein:

at least one of the first and second variable attenuators is provided as an electronically tunable attenuator controllable in conjunction with a change in bias voltage level applied to the transistor amplifier.

8. The linearizer circuit of claim 1, wherein:

at least one of the first and second RF signal paths includes a phase adjuster.

9. The linearizer circuit of claim 8, further comprising:

circuitry to electronically adjust a phase shift of at least one of the first and second RF signal paths.

10. The linearizer circuit of claim 9, wherein:

the circuitry to electronically adjust the phase shift of at least one of the first and second RF signal paths is configured to achieve a phase difference between the output signals of the first and second RF signal paths that result in signal cancellation in the combiner circuit.

11. The linearizer circuit of claim 1, further comprising:

circuitry for electronically adjusting an output amplitude level of at least one of the first and second RF signal paths; and

circuitry for electronically adjusting a phase shift of at least one of the first and second RF signal paths.

12. The linearizer circuit of claim 11, wherein:

the output of the combiner is to be coupled to the input of an RF power amplifier during operation of the linearizer circuit; and

the linearizer circuit further comprises a signed processing unit to determine an optimum condition based on an RF output signal of the RF power amplifier and to provide at least one control signal to the circuitry for electronically adjusting an output amplitude level and the circuitry for electronically adjusting a phase shift based on the optimum condition.

13. The linearizer circuit of claim 12, wherein:

the signal processing unit is configured to receive signals indicative of environmental conditions and to use the signals indicative of environmental conditions to determine the optimum condition.

14. The linearizer circuit of claim 1, wherein:

the linearizer circuit is configured to achieve a higher level of signal cancellation in the combiner when lower power input signals are applied to the linearizer and a lower level of signal cancellation in the combiner when higher power input signals are applied to the linearizer.

15. A method for use in linearizing operation of an RF power amplifier, comprising:

splitting a radio frequency (RF) input signal into first and second RF input signals;

providing the first RF input signal to a first RF signal path;

providing the second RF input signal to a second, different RF signal path, wherein the second RF signal path includes at least one active amplifier stage and the first RF signal path includes no active amplifier stages;

providing a first RF output signal at an output of the first RF signal path to a first input of a combiner;

providing a second RF output signal at an output of the second RF signal path to a second input of the combiner;

combining the first and second RF output signals in the combiner to generate a combined RF output signal at an output of the combiner; and

providing the combined RF output signal to the input of an RF power amplifier.

16. The method of claim 15, wherein:

providing the second RF input signal to the second RF signal path includes providing the second RF input signal to an RF signal path that includes a transistor amplifier having an odd number of active amplifier stages.

17. The method of claim 16, wherein;

providing the second RF input signal to the second RF signal path includes providing the second RF input signal to an RF signal path that includes a first variable attenuator positioned before the transistor amplifier and a second variable attenuator positioned after the transistor amplifier.

18. The method of claim 15, further comprising:

adjusting at least one of a phase shift and an output amplitude level associated with the first and second RF signal paths in a manner that results in maximal cancellation of the first and second RF output signals in the combiner under small signal conditions.

19. The method of claim 18, wherein;

adjusting is performed under the control of a signal processing device,

20. The method of claim 15, wherein:

splitting the RF input signal into first and second RF input signal comprises splitting the RF input signal to provide first and second RF input signals with substantially 90 degrees of phase difference between them; and

combining the first and second RF output signals comprises combining the signals in a combiner that takes two substantially opposite phase signals with an additional nominal 90 degrees of phase shift and combines thorn while cancelling the additional nominal 90 degrees of phase shift.

21. The method of claim 15, further comprising:

determining an optimum condition based on an RF output signal of the RF power amplifier; and

electronically adjusting an attenuation level in at least one of the first RF signal path and the second RF signal path, using control signals, based, at least in part, on the optimum condition.

22. The method of claim 21, further comprising:

electronically adjusting a phase shift in at least one of the first RF signal path and the second RF signal path, using control signals, based, at least in part on the optimum condition.

23. The method of claim 22, wherein:

the optimum condition is a condition that minimize sideband levels in the RF output signal of the RF power amplifier,

24. An amplification system, comprising;

a linearizer circuit comprising;

a divider circuit having an input and first and second outputs;

a first radio frequency (RF) signal path having an input and an output, the input of the first RF signal path being coupled to the first output of the divider circuit;

a second RF signal path having an input and an output, the input of the second RF signal path being coupled to the second output of the divider circuit; and

a combiner circuit coupled to the outputs of the first and second RF signal paths to combine output signals of the first and second RF signal paths to generate an output signal of the linearizer circuit; and

a power amplifier coupled to receive the output signal of the linearizer circuit;

wherein the power amplifier with the linearizer circuit operates more linearly than the power amplifier operating alone.

25. The amplification system of claim 24, wherein:

the first RF signal path includes a delay line having a predetermined length and the second RF signal path includes a transistor amplifier consisting of an odd number of gain stages,

26. The amplification system of claim 25, wherein:

the second RF signal path includes at least one adjustable attenuator.

27. The amplification system of claim 26, wherein:

the second RF signal path included at least one adjustable phase shifter.

28. The amplification system of claim 26, wherein:

the first RE signal path includes at least one adjustable phase shifter,

29. The amplification system of claim 24, wherein:

the gain versus input power curve of the linearizer circuit substantially complements the gain versus input power curve of the power amplifier to generate relatively linear gain for the amplification system overall.