INTEGRATED CIRCUIT DEVICE HAVING AN INJECTION-LOCKED OSCILLATOR

• US 20130241662A1
• Filed: 11/10/2011
• Published: 09/19/2013
• Est. Priority Date: 12/03/2010
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Aleksic, Marko, Leibowitz, Brian S.
• Granted Patent: US 9,287,880 B2
• Time in Patent Office: Days
• US Class Current: 331/173
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03L 1/00 Stabilisation of generator output against variations of physical values, e.g. power supply
• CPC Class Codes: H03L 7/083 the reference signal being additionally directly applied to the generator
• CPC Class Codes: H03L 7/24 using a reference signal directly applied to the generator

Abstract

A variable injection-strength injection-locked oscillator (ILO) is described. The variable injection-strength ILO can output an output clock signal based on an input clock signal. The variable injection-strength ILO can pause, restart, slow down, or speed up the output clock signal synchronously with respect to the input clock signal in response to receiving power mode information. Specifically, the variable injection-strength ILO can be operated under relatively strong injection when the input clock signal is paused, restarted, slowed down, or sped up.

Claims

1. A circuit, comprising:

an input to receive an input clock signal;

an output to output an output clock signal; and

a variable injection-strength injection-locked oscillator (ILO), wherein the variable injection-strength ILO generates the output clock signal based on the input clock signal and power mode information, and wherein the output clock signal pauses synchronously with respect to the input clock signal when the input clock signal pauses.

2. The circuit of claim 1, wherein the variable injection-strength ILO operates in one of multiple operating modes based on the power mode information;

wherein, in a first operating mode, the output clock signal is not capable of pausing synchronously with respect to the input clock signal when the input clock signal pauses; and

wherein, in a second operating mode, the output clock signal is capable of pausing synchronously with respect to the input clock signal when the input clock signal pauses.

3. The circuit of claim 2, wherein the variable injection-strength ILO generates an adjusted input signal based on the input signal, wherein the adjusted input signal is used as an injection signal in the variable injection-strength ILO, and wherein the amplitude of the adjusted input clock signal in the second operating mode is greater than the amplitude of the adjusted input clock signal in the first operating mode.

4. The circuit of claim 2, wherein an oscillation signal within the variable injection-strength ILO is perturbed based on the input clock signal, and wherein the amplitude of the oscillation signal in the second operating mode is less than the amplitude of the oscillation signal in the first operating mode.

5. The circuit of claim 2, wherein the input clock signal is injected at multiple injection points in the variable injection-strength ILO, and wherein the number of injection points in the second operating mode is greater than the number of injection points in the first operating mode.

6. The circuit of claim 2, further comprising control circuitry to operate the variable injection-strength ILO in the second operating mode or the first operating mode based on the power mode information.

7. The circuit of claim 6, wherein the control circuitry operates the variable injection-strength ILO in the second operating mode if the power mode information indicates that the circuit is about to transition between two power modes.

8. The circuit of claim 6, wherein the control circuitry operates the variable injection-strength ILO in the first operating mode if the power mode information indicates that the circuit has completed transitioning to a power mode.

9. The circuit of claim 6, wherein the control circuitry latches the output clock signal and powers down the variable injection-strength ILO after the output clock signal pauses synchronously with respect to the input clock signal.

10. The circuit of claim 9, wherein the circuitry powers up the variable injection-strength ILO and unlatches the output clock signal before the input clock signal is restarted.

30. The circuit of claim 1, further comprising memory controller circuitry to orchestrate data flow to and from one or more memory devices.

11. A circuit, comprising:

an input to receive an input clock signal;

an output to output an output clock signal; and

a variable injection-strength injection-locked oscillator (ILO), wherein the variable injection-strength ILO generates the output clock signal based on the input clock signal, wherein the variable injection-strength ILO has multiple operating modes including a first operating mode and a second operating mode, wherein the locking range of the variable injection-strength ILO in the first operating mode is less than the locking range of the variable injection-strength ILO in the second operating mode, and wherein the variable injection-strength ILO is operated in one of the multiple operating modes based on power mode information.

12. The circuit of claim 11, further comprising control circuitry to operate the variable injection-strength ILO in one of the multiple operating modes, wherein the control circuitry operates the variable injection-strength ILO in the second operating mode if the power mode information indicates that the circuit is about to transition between two power modes.

13. The circuit of claim 12, wherein the control circuitry operates the variable injection-strength ILO in the first operating mode if the power mode information indicates that the circuit has completed transitioning to a power mode.

14. The circuit of claim 11, wherein the variable injection-strength ILO generates an adjusted input clock signal based on the input clock signal, wherein the adjusted input clock signal is used as an injection clock signal in the variable injection-strength ILO, and wherein the amplitude of the adjusted input clock signal in the second operating mode is greater than the amplitude of the adjusted input clock signal in the first operating mode.

15. The circuit of claim 11, wherein an oscillation signal within the variable injection-strength ILO is perturbed based on the input clock signal, and wherein the amplitude of the oscillation signal in the second operating mode is less than the amplitude of the oscillation signal in the first operating mode.

16. The circuit of claim 11, wherein the input clock signal is injected at multiple injection points in the variable injection-strength ILO, and wherein the number of injection points in the second operating mode is greater than the number of injection points in the first operating mode.

31. The circuit of claim 11, further comprising memory controller circuitry to orchestrate data flow to and from one or more memory devices.

17-27. -27. (canceled)

28. A method, comprising:

receiving power mode information at a variable injection-strength injection-locked oscillator (ILO); and

increasing injection strength of the variable injection-strength ILO in response to the power mode information indicating that a circuit is about to transition between two power modes.

29. The method of claim 28, further comprising decreasing injection strength of the variable injection-strength ILO in response to the power mode information indicating that the circuit has completed transitioning to a power mode.