HIGH CAPACITANCE DENSITY METAL-INSULATOR-METAL CAPACITORS

• US 20130241939A1
• Filed: 04/24/2012
• Published: 09/19/2013
• Est. Priority Date: 03/16/2012
• Status: Abandoned Application

• Current Assignee: Snaptrack Incorporated (Qualcomm, Inc.)
• Original Assignee: Qualcomm MEMS Technologies Incorporated (Qualcomm, Inc.)
• Inventors: Lasiter, Jon Bradley, Shenoy, Ravindra V., Black, Justin Phelps, Kidwell, Donald William
• Application Number:
  US13/454,949
• Publication Number:
  US 20130241939A1
• Time in Patent Office: Days
• US Class Current: 345/501
• CPC Class Codes: H01G 4/1209 characterised by the ceramic dielectric material H01G4/1272, H01G4/1281 take precedence
• CPC Class Codes: H01G 4/33 Thin- or thick-film capacitors thin- or thick-film circuits H01L27/00; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor H01L28/40
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10T 29/49124 On flat or curved insulated base, e.g., printed circuit, etc.

Abstract

This disclosure provides systems, methods, and apparatus for high capacitance density metal-insulator-metal capacitors. In one aspect, an apparatus may include a first base metal layer on a first side of a substrate. A first polymer layer may be disposed on the first base metal layer and on the first side of the substrate. The first polymer layer may define a first plurality of vias though the first polymer layer, the first plurality of vias exposing portions of the first base metal layer. A first electrode layer may be disposed on the first polymer layer. The first electrode layer may contact the portions of the first base metal layer. A first dielectric layer may be disposed on the first electrode layer. A second electrode layer may be disposed on the first dielectric layer. The first dielectric layer may electrically isolate the first electrode layer from the second electrode layer.

Claims

1. An apparatus comprising:

a first base metal layer on a first side of a substrate;

a first polymer layer disposed on the first base metal layer and on the first side of the substrate, the first polymer layer defining a first plurality of vias though the first polymer layer exposing portions of the first base metal layer;

a first electrode layer disposed on the first polymer layer, the first electrode layer contacting the portions of the first base metal layer;

a first dielectric layer disposed on the first electrode layer; and

a second electrode layer disposed on the first dielectric layer, the first dielectric layer electrically isolating the first electrode layer from the second electrode layer.

2. The apparatus of claim 1, wherein a first via of the first plurality of vias in the first polymer layer has an aspect ratio of at least about 10 to 1.

3. The apparatus of claim 1, wherein a first via of the first plurality of vias in the first polymer layer has an opening on a surface of the first polymer layer of about 100 nanometers to 500 nanometers, and wherein the first polymer layer is about 1 micron to 5 microns thick.

4. The apparatus of claim 1, wherein a first via of the first plurality of vias in the first polymer layer has an opening on a surface of the first polymer layer of about 1 micron to 25 microns, and wherein the first polymer layer is about 10 microns to 250 microns thick.

5. The apparatus of claim 1, wherein the first base metal layer, the first electrode layer, and the second electrode layer include aluminum.

6. The apparatus of claim 1, wherein the first base metal layer reduces the equivalent series resistance of the apparatus.

7. The apparatus of claim 1, wherein the substrate is a glass substrate.

8. The apparatus of claim 1, the substrate defining at least one through via in the substrate.

9. The apparatus of claim 8, wherein the substrate is an interposer, and wherein the through via includes a conductive material configured to electrically connect a first electronic component on the first side of the substrate to a second electronic component on a second side of the substrate opposite to the first side, wherein the second electronic component is disposed on a second substrate or a printed circuit board (PCB).

10. The apparatus of claim 1, further comprising:

a second base metal layer on a second side of the substrate;

a second polymer layer disposed on the second base metal layer and on the second side of the substrate, the second polymer layer defining a second plurality of vias though the second polymer layer exposing portions of the second base metal layer;

a third electrode layer disposed on the second polymer layer, the third electrode layer contacting the portions of the second base metal layer;

a second dielectric layer disposed on the third electrode layer;

a fourth electrode layer disposed on the second dielectric layer, the second dielectric layer electrically isolating the third electrode layer from the fourth electrode layer;

a first connection electrically connecting the first and the third electrode layers; and

a second connection electrically connecting the second and the fourth electrode layers.

11. The apparatus of claim 10, wherein the first connection includes a first via though the substrate, and wherein the second connection includes a second via through the substrate.

12. The apparatus of claim 10, wherein a first via of the second plurality of vias in the second polymer layer has an aspect ratio of at least about 10 to 1.

13. A system comprising the apparatus of claim 1, the system further comprising:

a display;

a processor that is configured to communicate with the display, the processor being configured to process image data; and

a memory device that is configured to communicate with the processor.

14. The system of claim 13, further comprising:

a driver circuit configured to send at least one signal to the display; and

a controller configured to send at least a portion of the image data to the driver circuit.

15. The system of claim 13, further comprising:

an image source module configured to send the image data to the processor.

16. The system of claim 15, wherein the image source module includes at least one of a receiver, transceiver, and transmitter.

17. The system of claim 13, further comprising:

an input device configured to receive input data and to communicate the input data to the processor.

18. An apparatus comprising:

a base metal layer on a substrate;

a polymer layer disposed on the base metal layer and on the substrate;

a first electrode layer disposed on the polymer layer;

a second electrode layer;

means for exposing portions of the base metal layer, the first electrode layer contacting the portions of the base metal layer; and

means for electrically isolating the first electrode layer from the second electrode layer.

19. The apparatus of claim 18, wherein the means for exposing portions of the base metal layer increases a surface area between the first electrode layer and the second electrode layer.

20. The apparatus of claim 18, wherein the base metal layer reduces the equivalent series resistance of the apparatus.

21. A method comprising:

depositing a base metal layer on a surface of a substrate;

forming a polymer layer on the base metal layer and on the surface of the substrate;

patterning a design in the polymer layer;

depositing a first electrode layer on the polymer layer and on exposed portions of the base metal layer;

depositing a dielectric layer on the first electrode layer; and

depositing a second electrode layer on the dielectric layer.

22. The method of claim 21, wherein the patterning includes embossing.

23. The method of claim 21, wherein the patterning includes a nanoimprinting process.

24. The method of claim 23, wherein the nanoimprinting process includes:

heating the polymer layer;

pressing a mold into the polymer layer;

cooling the polymer layer; and

removing the mold from the polymer layer.

25. The method of claim 23, wherein the nanoimprinting process includes:

heating the polymer layer;

pressing a mold into the polymer layer;

treating the polymer layer with an ultraviolet light; and

removing the mold from the polymer layer.

26. The method of claim 21, wherein the design in the polymer layer includes a plurality of vias, a first via of the plurality of vias having an aspect ratio of at least about 10 to 1.