METHOD OF FABRICATING FIN-FIELD EFFECT TRANSISTORS (FINFETS) HAVING DIFFERENT FIN WIDTHS

• US 20130244392A1
• Filed: 02/28/2013
• Published: 09/19/2013
• Est. Priority Date: 03/19/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Jongwook, OH, Chang Woo, Min, Shincheol, Lee, Choongho
• Granted Patent: US 8,987,100 B2
• Time in Patent Office: Days
• US Class Current: 438/299
• CPC Class Codes: H01L 21/02107 Forming insulating materials on a substrate
• CPC Class Codes: H01L 21/302 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Provided are methods of forming field effect transistors. The method includes preparing a substrate with a first region and a second region, forming fin portions on the first and second regions, each of the fin portions protruding from the substrate and having a first width, forming a first mask pattern to expose the fin portions on the first region and cover the fin portions on the second region, and changing widths of the fin portions provided on the first region.

Claims

1. A method of fabricating an integrated circuit device, the method comprising:

forming fin-shaped transistor channel regions protruding from first and second regions of a substrate; and

selectively altering respective widths of ones of the fin-shaped transistor channel regions protruding from the first region while maintaining respective widths of ones of the fin-shaped transistor channel regions protruding from the second region.

2. The method of claim 1, wherein selectively altering comprises one of etching or growing a semiconductor layer on sidewalls of the ones of the fin-shaped transistor channel regions protruding from the first region, and wherein the respective widths of the ones of the fin-shaped transistor channel regions protruding from the first and second regions are substantially similar prior to selectively altering the respective widths of the ones of the fin-shaped transistor channel regions protruding from the first region.

3. The method of claim 2, wherein, after selectively altering the respective widths of the ones of the fin-shaped transistor channel regions protruding from the first region, respective heights of the ones of the fin-shaped transistor channel regions protruding from the first and second regions may be substantially similar.

4. The method of claim 2, wherein, after selectively altering the respective widths of the ones of the fin-shaped transistor channel regions protruding from the first region, surfaces of the first and second regions are non-coplanar.

5. The method of claim 2, further comprising:

doping the substrate prior to selectively altering the respective widths of the ones of the first fin-shaped transistor channel regions,

wherein, after selectively altering the respective widths of the ones of the fin-shaped transistor channel regions protruding from the first region, the ones of the fin-shaped transistor channel regions protruding from the first region have different doping concentrations or doping amounts than the ones of the fin-shaped transistor channel regions protruding from the second region.

6. A method of forming field effect transistors, comprising:

forming fin portions on first and second regions of a substrate, each of the fin portions protruding from the substrate;

forming a first mask pattern to expose the fin portions on the first region and cover the fin portions on the second region; and

changing widths of the fin portions provided on the first region.

7. The method of claim 6, wherein changing the widths of the fin portions comprises growing a semiconductor layer on the fin portions.

8. The method of claim 6, further comprising forming device isolation layers on lower sidewalls of the fin portions,

wherein the semiconductor layer is formed before forming the device isolation layers.

9. The method of claim 8, wherein the forming of the fin portions comprises:

forming second mask patterns on the substrate; and

etching the substrate using the second mask patterns as an etch mask,

wherein the semiconductor layer is formed on sidewalls of the fin portions and on a top surface of the substrate exposed by the first and second mask patterns.

10. The method of claim 7, further comprising forming device isolation layers on lower sidewalls of the fin portions,

wherein the first mask pattern and the semiconductor layer are formed after forming the device isolation layers.

11. The method of claim 10, wherein the semiconductor layer is formed on upper sidewalls and top surfaces of the fin portions exposed by the device isolation layers and the first mask pattern.

12. The method of claim 7, wherein the semiconductor layer comprises a material having a different lattice constant and/or bandgap from the fin portions.

13. The method of claim 6, wherein changing the widths of the fin portions comprises etching the fin portions provided on the first region.

14. The method of claim 13, further comprising forming device isolation layers on lower sidewalls of the fin portions,

wherein the device isolation layers are formed after etching the fin portions.

15. The method of claim 14, wherein the forming the fin portions comprises:

forming second mask patterns on the substrate; and

etching the substrate using the second mask patterns as an etch mask,

wherein etching the fin portions comprises etching sidewalls of the fin portions and a top surface of the substrate exposed by the first and second mask patterns.

16. The method of claim 13, further comprising forming device isolation layers on lower sidewalls of the fin portions,

wherein the device isolation layers are formed before etching the fin portions, and wherein etching the fin portions comprises etching top surfaces and upper sidewalls of the fin portions exposed by the first mask pattern and the device isolation layers.

17. The method of claim 6, wherein forming the fin portions comprises:

forming second mask patterns on the substrate; and

etching the substrate using the second mask patterns as an etch mask,

wherein forming the second mask patterns comprises;

forming third mask patterns on the substrate;

performing a spacer-forming process to form the second mask patterns on sidewalls of the third mask patterns; and

removing the third mask patterns.

18. The method of claim 17, wherein respective widths of the second mask patterns are substantially equal.

19. A method of forming field effect transistors, comprising:

forming first mask patterns on a substrate including first and second regions, the first mask patterns having a first width and being spaced apart from each other by a second width different from the first width;

forming second mask patterns on the substrate between the first mask patterns;

removing the first mask patterns from the second region;

removing the second mask patterns from the first region; and

etching the substrate using the first mask patterns on the first region and the second mask patterns on the second region as an etch mask to define first and second fin-shaped transistor channel regions of different widths protruding from the first and second regions, respectively.

20. The method of claim 19, wherein forming the first mask patterns comprises:

forming third mask patterns on the substrate;

performing a spacer-forming process to form the first mask patterns on sidewalls of the third mask patterns; and

removing the third mask patterns.