METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING DUAL GATE DIELECTRIC LAYER

• US 20130244414A1
• Filed: 03/12/2013
• Published: 09/19/2013
• Est. Priority Date: 03/15/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yoon, Boun, Han, Jeongnam, Song, Myung Geun, Ko, Ki-Hyung, Jeon, Hayoung
• Granted Patent: US 8,859,371 B2
• Time in Patent Office: Days
• US Class Current: 438/591
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

Methods for manufacturing a semiconductor device having a dual gate dielectric layer may include providing a substrate including first and second regions, forming a first gate dielectric layer having a first thickness on the substrate, forming an interlayer insulating layer including first and second trenches exposing the first gate dielectric layer in the first and second regions, forming a sacrificial layer on the interlayer insulating layer and bottoms of the first and second trenches, forming a sacrificial pattern exposing the first gate dielectric layer of the bottom of the first trench, removing the first gate dielectric layer of the bottom of the first trench, forming a second gate dielectric layer having a second thickness on the bottom of the first trench, removing the sacrificial pattern, and forming a gate electrode on each of the first and second gate dielectric layers.

Claims

1. A method of manufacturing a semiconductor device, comprising:

providing a substrate including a first region and a second region;

forming a first gate dielectric layer having a first thickness on the substrate;

forming an interlayer insulating layer on the substrate, the interlayer insulating layer including a first trench exposing the first gate dielectric layer of the first region and a second trench exposing the first gate dielectric layer of the second region;

forming a sacrificial layer on the interlayer insulating layer and bottoms of the first and second trenches;

forming a mask pattern covering the second trench of the second region on the sacrificial layer;

removing the sacrificial layer in the first region using the mask pattern as an etch mask to form a sacrificial pattern exposing the first gate dielectric layer of the bottom of the first trench;

removing the first gate dielectric layer of the bottom of the first trench to expose the substrate;

removing the mask pattern;

removing the sacrificial pattern;

forming a second gate dielectric layer having a second thickness on the bottom of the first trench; and

forming a gate electrode on each of the first gate dielectric layer and the second gate dielectric layer.

2. The method of claim 1, wherein forming the interlayer insulating layer including the first trench and the second trench comprises:

forming a first dummy gate pattern on the first gate dielectric layer of the first region;

forming a second dummy gate pattern on the first gate dielectric layer of the second region;

forming the interlayer insulating layer exposing top surfaces of the first dummy gate pattern and the second dummy gate pattern; and

removing the first dummy gate pattern and the second dummy gate pattern.

3. The method of claim 2, further comprising:

forming a spacer on sidewalls of each of the first and second dummy gate patterns.

4. The method of claim 1, further comprising:

forming a high-k dielectric material between each of the gate electrodes and each of the first and second gate dielectric layers.

5. The method of claim 1, wherein the sacrificial layer includes at least one of a silicon oxide layer, a silicon nitride layer, a poly-crystalline silicon layer, and a metal layer.

6. The method of claim 1, wherein the sacrificial layer is formed by an atomic layer deposition (ALD) method.

7. The method of claim 1, wherein removing the sacrificial layer in the first region using the mask pattern as the etch mask is performed using a solution including at least one of hydrogen fluoride, phosphoric acid, sulfuric acid, hydrogen peroxide, ammonium hydroxide, hydrogen chloride, and amine.

8. The method of claim 1, wherein removing the first gate dielectric layer of the bottom of the first trench to expose the substrate is performed by a chemical oxide removal (COR) method using a HF gas and a NH₃ gas, or a chemical etching by plasma (CEP) method using NH₃ and NF₃ remote plasma.

9. The method of claim 1, including forming the mask pattern of a photoresist.

10. The method of claim 9, wherein removing the mask pattern is performed using an organic stripper, sulfuric acid, or a mixture solution of sulfuric acid and hydrogen peroxide.

11. The method of claim 10, including forming a chemical oxide layer on the substrate exposed by the first trench when the mask pattern is removed;

and

removing the chemical oxide layer simultaneously with the sacrificial pattern when the sacrificial pattern is removed.

12. The method of claim 1, including forming the first gate dielectric layer by a dry oxidation method or a radical oxidation method.

13. The method of claim 1, including forming the second gate dielectric layer by a chemical oxidation method.

14. The method of claim 1, wherein the first thickness of the first gate dielectric layer is greater than the second thickness of the second gate dielectric layer.

15. The method of claim 1, wherein the gate electrode includes at least one of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, copper, aluminum and any combination thereof.

16. The method of claim 1, wherein removing the sacrificial pattern is performed simultaneously with the formation of the second gate dielectric layer having the second thickness on the bottom of the first trench.

17. The method of claim 16, including forming the sacrificial layer of titanium nitride, wherein forming the second gate dielectric layer is performed using a solution including ammonium hydroxide and hydrogen peroxide or a solution including ozone.

18. A method for manufacturing a semiconductor device, comprising:

providing a substrate including a first region and a second region;

forming a first gate dielectric layer having a first thickness on the substrate;

forming an interlayer insulating layer on the substrate, the interlayer insulating layer including a first trench exposing the first gate dielectric layer of the first region and a second trench exposing the first gate dielectric layer of the second region;

forming a sacrificial layer on the interlayer insulating layer and bottoms of the first and second trenches;

forming a mask pattern covering the second trench of the second region on the sacrificial layer;

removing the sacrificial layer in the first region using the mask pattern as an etch mask to form a sacrificial pattern covering the second trench;

removing the mask pattern;

removing the first gate dielectric layer of the bottom of the first trench using the sacrificial pattern as an etch mask to expose the substrate;

forming a second gate dielectric layer having a second thickness on the bottom of the first trench; and

forming a gate electrode on each of the first gate dielectric layer and the second gate dielectric layer.

19. The method of claim 18, further comprising:

forming a high-k dielectric material between each of the gate electrodes and each of the first and second gate dielectric layers.

20. A method for manufacturing a semiconductor device, comprising:

providing a substrate including a first region and a second region;

forming a first gate dielectric layer having a first thickness on the substrate;

forming an interlayer insulating layer on the substrate, the interlayer insulating layer including a first trench exposing the first gate dielectric layer of the first region and a second trench exposing the first gate dielectric layer of the second region;

forming a sacrificial layer on the interlayer insulating layer and bottoms of the first and second trenches;

forming a mask pattern covering the second trench of the second region on the sacrificial layer;

removing the sacrificial layer in the first region using the mask pattern as an etch mask to form a sacrificial pattern;

removing an upper portion of the first gate dielectric layer of the bottom of the first trench to form a second gate dielectric layer having a second thickness smaller than the first thickness; and

forming a gate electrode on each of the first gate dielectric layer and the second gate dielectric layer.

21. A method for manufacturing a semiconductor device having a dual gate dielectric layer, comprising:

providing a substrate including first and second regions;

forming a first gate dielectric layer having a first thickness on the substrate;

forming an interlayer insulating layer including first and second trenches exposing the first gate dielectric layer in the first and second regions;

forming a sacrificial layer on the interlayer insulating layer and bottoms of the first and second trenches;

forming a sacrificial pattern exposing the first gate dielectric layer of the bottom of the first trench;

forming a second gate dielectric layer having a second thickness on the bottom of the first trench;

removing the sacrificial pattern; and

forming a gate electrode on each of the first and second gate dielectric layers.

22. The method of claim 21, wherein the second dielectric layer is thinner than the first dielectric layer.

23. The method of claim 21, further comprising:

forming a high-k dielectric material between each of the gate electrodes and each of the first and second gate dielectric layers.