METHOD AND SYSTEM FOR CONTROLLING POWER

• US 20130246826A1
• Filed: 04/30/2013
• Published: 09/19/2013
• Est. Priority Date: 04/22/2010
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Hollingworth, Gordon
• Granted Patent: US 9,317,103 B2
• Time in Patent Office: Days
• US Class Current: 713/324
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and system for controlling power is provided. The system is configured to selectively control a plurality of power control domains. The system may be configured to process audio data in at least one of the domains. The system may be configured to output audio data, while one or more of the power control domains is suspended.

Claims

1. A method for controlling power, the method comprising:

in an integrated circuit comprising a multimedia processor, said multimedia processor comprising an audio interface and a processing unit;

decoding coded audio data with the processing unit to generate decoded audio data;

storing the decoded audio in memory;

powering down the processing unit; and

providing, with the audio interface, the decoded audio data from the memory to an output, while the processing unit is powered down.

2. The method according to claim 1, further comprising storing processor states for the processing unit in memory, before powering down the processing unit.

3. The method according to claim 1, wherein the processing unit is powered down in response to a first amount of audio data being decoded.

4. The method according to claim 1, further comprising powering up the processing unit in response to an amount of decoded audio data to be transferred falling below a threshold amount of decoded audio data.

5. The method according to claim 4, further comprising retrieving stored processor states from the memory in response to the amount of decoded audio data to be transferred falling below a threshold amount of decoded audio data.

6. The method according to claim 5, further comprising decoding a burst of coded audio data in response to the amount of decoded audio data to be transferred falling below a threshold amount of decoded audio data.

7. The method according to claim 1, wherein the processing unit includes a vector processing unit, a graphics processing unit, and a video coder.

8. The method according to claim 1, wherein the processing unit is a video processing core and power is removed from the entire video processing core during power down.

9. The system for controlling power, the system comprising:

an integrated circuit including a multimedia processor having a plurality of power control domains, each power control domain being configured for independent power control from each other power control domain of the plurality of power domains, the plurality of power control domains comprising an interface domain configured to process audio output while each other power control domain is suspended.

10. The system according to claim 9, wherein the plurality of power control domains includes an image domain and the interface domain is configured to process the audio output while the image domain is suspended.

11. The system according to claim 9, wherein the plurality of power control domains includes a graphics domain the interface domain is configured to process the audio output while the graphics domain is suspended.

12. The system according to claim 9, wherein the plurality of power control domains includes an audio domain the interface domain is configured to process the audio output while the audio domain is suspended.

13. The system according to claim 12, wherein power is removed from the audio domain while the audio domain is suspended.

14. The system according to claim 13, wherein audio domain comprises a vector processing unit, a direct memory access controller, and a display driver.

15. The system according to claim 12, wherein the audio domain includes a processing unit for decoding audio data.

16. The system according to claim 15, wherein the processing unit is configured to store processor states in memory, before suspension of the audio domain.

17. The system according to claim 16, wherein the audio domain is suspended in response to a first amount of audio data being decoded.

18. The system according to claim 17, wherein the audio domain configured to wake-up in response to an amount of decoded audio data to be transferred falling below a threshold amount of decoded audio data.

19. The system according to claim 18, wherein the processing unit is configured to retrieve processor states in response to audio domain waking-up.

20. In a computer readable storage medium having stored therein instructions executable by a programmed processor for controlling power, the storage medium comprising instructions for:

selectively controlling a plurality of power control domains;

decoding, within an audio domain of the plurality of power control domains, coded audio data to generate decoded audio data;

suspending the plurality of power control domains; and

providing the decoded audio data to an output, while the plurality of power control domains is suspended.