INTEGRATED CIRCUIT AND METHOD FOR MONITORING BUS STATUS IN INTEGRATED CIRCUIT

• US 20130246859A1
• Filed: 01/30/2013
• Published: 09/19/2013
• Est. Priority Date: 03/01/2012
• Status: Active Grant

• Current Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Inventors: Sun, Xingguo, Tang, Wei, Wang, Haijun
• Granted Patent: US 9,201,753 B2
• Time in Patent Office: Days
• US Class Current: 714/47.1
• CPC Class Codes: G06F 11/3027 where the computing system component is a bus
• CPC Class Codes: G06F 11/3055 Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available error or fault processing without redundancy G06F11/0703; error detection or correction by redundancy in data representation G06F11/08; error detection or correction by redundancy in operation G06F11/14; error detection or correction by redundancy in hardware G06F11/16
• CPC Class Codes: G06F 11/3409 for performance assessment

Abstract

Embodiments of the present invention disclose an integrated circuit and a method for monitoring a bus status in the integrated circuit. Multiple status detectors and a top layer monitor are disposed in the integrated circuit. Each status detector in the multiple status detectors is used to read status data on a branch bus that is coupled to each status detector in the multiple status detectors, and then the top layer monitor collects the status data from each status detector, and outputs the status data through an interface.

Claims

1. An integrated circuit, comprising:

a processor, a host bus, multiple branch buses, multiple status detectors, a top layer monitor, and an interface;

wherein

the multiple branch buses are coupled to the processor through the host bus;

the host bus is configured to transmit data from the multiple branch buses to the processor;

the processor is configured to perform data processing;

each status detector in the multiple status detectors is coupled to a branch bus in the multiple branch buses respectively, and is configured to read status data on the branch bus that is coupled to each status detector, and upload the status data to the top layer monitor; and

the top layer monitor is configured to collect the status data from each status detector, and output the status data through the interface.

2. The integrated circuit according to claim 1, wherein the top layer monitor comprises at least one buffer, configured to buffer the status data from each status detector.

3. The integrated circuit according to claim 2, wherein the top layer monitor comprises:

a processing unit, configured to separately pack the status data from each status detector to obtain packed status data from each status detector, and output the packed status data from each status detector through the interface, wherein the packed status data from each status detector comprises an identifier that corresponds to each status detector, or

configured to group the status data from the multiple status detectors into different types of status data, pack the same type of status data, and output the same type of packed status data through the interface.

4. The integrated circuit according to claim 1, wherein each status detector is configured to pack the status data, and upload packed status data to the top layer monitor.

5. The integrated circuit according to claim 1, wherein each status detector comprises:

a storage, configured to store a status access request on the branch bus that is coupled to each status detector in the integrated circuit;

a control unit, configured to read the status access request that is from the storage, and trigger an operation of reading the status data on the branch bus that is coupled to each status detector; and

a reporter, configured to upload the read status data to the top layer monitor.

6. The integrated circuit according to claim 1, wherein each status detector periodically reads the status data on the branch bus that is coupled to each status detector.

7. The integrated circuit according to claim 6, wherein the branch bus in the multiple branch buses is coupled to the host bus through another branch bus.

8. A method for monitoring a bus status in an integrated circuit, comprising:

reading, by each status detector in multiple status detectors, status data on a branch bus that is coupled to each status detector in the multiple status detectors; and

collecting, by a top layer monitor, the status data from each status detector, and outputting the status data through an interface, wherein

the branch buses are coupled to a processor through a host bus;

the host bus is configured to transmit data from the branch buses to the processor; and

the processor is configured to perform data processing.

9. The method according to claim 8, wherein the collecting, by the top layer monitor, the status data from each status detector comprises:

buffering the status data from each status detector.

10. The method according to claim 9, wherein the outputting the status data through the interface comprises:

separately packing the status data from each status detector;

or

grouping the status data from the multiple status detectors into different types of status data, and packing the same type of status data; and

sending packed status data to the interface.