STATISTICAL DISTRIBUTION BASED VARIABLE-BIT ERROR CORRECTION CODING

• US 20130246878A1
• Filed: 04/19/2012
• Published: 09/19/2013
• Est. Priority Date: 03/15/2012
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: PANCHOLI, DEEPAK, D'ABREU, MANUEL ANTONIO, NAIR, RADHAKRISHNAN, SKALA, STEPHEN
• Granted Patent: US 8,862,967 B2
• Time in Patent Office: Days
• US Class Current: 714/752
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: H03M 13/00 Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes error detection or error correction for analogue/digital, digital/analogue or code conversion H03M1/00 – H03M11/00; specially adapted for digital computers G06F11/08; for information storage based on relative movement between record carrier and transducer G11B, e.g. G11B20/18; for static stores G11C
• CPC Class Codes: H03M 13/21 Non-linear codes, e.g. m-bit data word to n-bit code word [mBnB] conversion with error detection or error correction
• CPC Class Codes: H03M 13/25 Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] modulation codes H03M13/31
• CPC Class Codes: H03M 13/255 with Low Density Parity Check [LDPC] codes
• CPC Class Codes: H03M 13/258 with turbo codes, e.g. Turbo Trellis Coded Modulation [TTCM]
• CPC Class Codes: H03M 13/2927 Decoding strategies
• CPC Class Codes: H03M 13/35 Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
• CPC Class Codes: H03M 13/6318 using variable length codes
• CPC Class Codes: H03M 7/40 Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code
• CPC Class Codes: H03M 7/4031 Fixed length to variable length coding
• CPC Class Codes: H03M 7/405 Tree adaptation
• CPC Class Codes: H03M 7/4093 Variable length to variable length coding
• CPC Class Codes: H04N 19/13 Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
• CPC Class Codes: H04N 19/91 Entropy coding, e.g. variable length coding [VLC] or arithmetic coding

Abstract

A method may be performed at a data storage device that includes a memory and a controller. The method includes providing user data to a variable-bit error correction coding (ECC) encoder. The ECC encoder generates a first set of parity bits. A first number of parity bits in the first set of parity bits is determined based on stored counts of read errors. The method also includes storing the user data and the first set of parity bits to a memory of the data storage device.

Claims

1. A method comprising:

in a data storage device, performing;

providing user data to a variable-bit error correction coding (ECC) encoder that generates a first set of parity bits, wherein a first number of parity bits in the first set of parity bits is determined based on stored counts of read errors; and

storing the user data and the first set of parity bits to a memory of the data storage device.

2. The method of claim 1, wherein the first number of parity bits is selected to correspond to a threshold probability of error correction based on the stored counts of read errors.

3. The method of claim 2, wherein the threshold probability corresponds to an approximately 95 percent likelihood of successful error correction using the first number of parity bits.

4. The method of claim 1, further comprising storing a second set of parity bits based on the user data, wherein a second number of parity bits in the second set is greater than the first number of parity bits.

5. The method of claim 4, wherein the second set of parity bits is generated by the variable-bit ECC encoder.

6. The method of claim 4, wherein the second set of parity bits is generated by a second ECC encoder.

7. The method of claim 4, wherein the second set of parity bits corresponds to a larger correction capacity than the first set of parity bits.

8. The method of claim 4, further comprising:

reading the user data and the first set of parity bits from the memory;

initiating a first decode operation using the user data and the first set of parity bits; and

in response to the first decode operation failing, initiating a second decode operation using the user data and the second set of parity bits.

9. The method of claim 1, further comprising updating the stored counts of read errors each time data is read from the memory and a corresponding error count is determined.

10. The method of claim 1, wherein the stored counts of read errors are initialized by retrieving preloaded data written to the memory prior to a first storage of user-provided data to the memory.

11. The method of claim 1, wherein the stored counts of read errors are initialized by:

encoding data to be stored to the memory using a largest number of parity bits of the variable-bit ECC encoder;

upon reading the data from the memory, storing counts of read errors detected during ECC decoding using the largest number of parity bits; and

in response to storing a first predetermined number of the counts of read errors, determining the first number of parity bits.

12. The method of claim 11, wherein the encoded data includes test data generated by a controller of the data storage device.

13. The method of claim 11, wherein the encoded data includes user-provided data.

14. A data storage device comprising:

a memory; and

a controller configured to provide user data to a variable-bit error correction coding (ECC) encoder to generate a first set of parity bits and to store the user data and the first set of parity bits to the memory, wherein a first number of parity bits in the first set of parity bits is determined based on stored counts of read errors.

15. The data storage device of claim 14, wherein the first number of parity bits is selected to correspond to a threshold probability of error correction based on the stored counts of read errors.

16. The data storage device of claim 14, wherein the controller is further configured to store a second set of parity bits based on the user data, wherein a second number of parity bits in the second set is greater than the first number of parity bits.

17. The data storage device of claim 16, wherein the controller is configured to initiate an encoding operation at the variable-bit ECC encoder to generate the second set of parity bits.

18. The data storage device of claim 16, further comprising a second ECC encoder and wherein the controller is configured to initiate an encoding operation at the second ECC encoder to generate the second set of parity bits.

19. The data storage device of claim 16, wherein the controller is configured to read the user data and the first set of parity bits from the memory and to initiate a first decode operation using the user data and the first set of parity bits and, in response to the first decode operation failing, to initiate a second decode operation using the user data and the second set of parity bits.

20. The data storage device of claim 16, wherein the second set of parity bits corresponds to a larger correction capacity than the first set of parity bits.

21. The data storage device of claim 14, wherein the controller is configured to update the stored counts of read errors each time data is read from the memory and a corresponding error count is determined.

22. The data storage device of claim 14, wherein the stored counts of read errors are initialized by retrieving preloaded data written to the memory prior to a first storage of user-provided data to the memory.

23. The data storage device of claim 14, wherein the memory includes a flash memory.