DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

• US 20130246883A1
• Filed: 11/14/2011
• Published: 09/19/2013
• Est. Priority Date: 11/22/2010
• Status: Active Grant

• Current Assignee: Saturn Licensing LLC (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Shinya, Osamu, Yokokawa, Takashi, Michael, Lachlan Bruce
• Granted Patent: US 9,172,497 B2
• Time in Patent Office: Days
• US Class Current: 714/752
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/152 Bose-Chaudhuri-Hocquenghem [BCH] codes
• CPC Class Codes: H03M 13/253 with concatenated codes
• CPC Class Codes: H03M 13/255 with Low Density Parity Check [LDPC] codes
• CPC Class Codes: H03M 13/618 Shortening and extension of codes
• CPC Class Codes: H03M 13/6362 by puncturing
• CPC Class Codes: H03M 13/6552 DVB-T2
• CPC Class Codes: H04L 1/004 by using forward error control H04L1/0618 takes precedence; coding, decoding or code conversion, for error detection or correction H03M13/00
• CPC Class Codes: H04L 1/0043 Realisations of complexity reduction techniques, e.g. use of look-up tables
• CPC Class Codes: H04L 1/0052 Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0065 Serial concatenated codes
• CPC Class Codes: H04L 1/0068 by puncturing
• CPC Class Codes: H04L 1/0072 Error control for data other than payload data, e.g. control data

Abstract

A data processing device and a data processing method that can readily process control data having its PAPR improved. In a transmission device, a padder pads control data necessary for demodulation with zeros as dummy data, and a scrambler scrambles the padded control data (post-padding control data). A replacement unit replaces scrambled dummy data in the scrambled post-padding control data with the dummy data, and a BCH encoder and an LDPC encoder perform BCH encoding and LDPC encoding as error correction encoding on the replacement data obtained through the replacement. A shortening unit performs shortening by deleting the dummy data contained in the LDPC code and puncturing the parity bits of the LDPC code. The device can be applied in cases where control data is subjected to error correction encoding and is then transmitted, for example.

Claims

1. A data processing device comprising:

a padding means that pads control data with dummy data, the control data being necessary for demodulation;

a scrambling means that scrambles post-padding control data, the post-padding control data being the padded control data;

a replacement means that generates replacement data by replacing scrambled dummy data in the scrambled post-padding control data with the dummy data; and

an error correction encoding means that performs error correction encoding on the replacement data.

3. The data processing device according to claim 1, wherein the error correction encoding means determines a parity bit for data to be subjected to the error correction encoding, and adds the parity bit to the data to be subjected to the error correction encoding, to obtain an error correcting code,

the data processing device further comprising

a shortening means that performs shortening by deleting the dummy data from the error correcting code and puncturing a parity bit of the error correcting code.

4. The data processing device according to claim 1, wherein the padding means performs the padding with the dummy data, to adjust a data length of padded data to a target data length of the error correction encoding.

5. The data processing device according to claim 1, wherein

the scrambling means includes:

a register group formed with fifteen registers connected in series, a register in a later stage latching bits latched by a register in a previous stage;

a first EXOR circuit that calculates an exclusive OR between bits latched by a fourteenth register and bits latched by a fifteenth register; and

a second EXOR circuit that calculates an exclusive OR between an output of the first EXOR circuit and data to be scrambled, and outputs a result of the calculation as scrambled data,

a first register of the register group latches the output of the first EXOR circuit, and

bits 1, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, and 0 are set as initial values in the first through fifteenth registers of the register group, respectively.

6. The data processing device according to claim 1, wherein the control data is one of:

first data necessary for demodulating actual data;

second data necessary for demodulating the first data; and

the first and second data.

7. The data processing device according to claim 1, wherein a new frame containing the error correcting code obtained through the error correction encoding is multiplexed with a T2 frame specified in DVB-T.2 and is transmitted.

8. The data processing device according to claim 1, wherein

a preamble is placed at the top of each of the T2 frame and the new frame,

the preamble of the T2 frame contains information identifying the T2 frame, and

the preamble of the new frame contains information identifying the new frame.

2. A data processing device comprising:

a scrambling means that scrambles control data necessary for demodulation;

a padding means that pads the scrambled control data with dummy data; and

an error correction encoding means that performs error correction encoding on post-padding scrambled data formed by padding the scrambled control data with the dummy data.

9. A data processing method comprising the steps of:

padding control data with dummy data, the control data being necessary for demodulation;

scrambling post-padding control data, the post-padding control data being the padded control data;

generating replacement data by replacing scrambled dummy data in the scrambled post-padding control data with the dummy data; and

performing error correction encoding on the replacement data.

10. A data processing method comprising the steps of:

scrambling control data necessary for demodulation;

padding the scrambled control data with dummy data; and

performing error correction encoding on post-padding scrambled data formed by padding the scrambled control data with the dummy data.

11. A data processing device comprising:

an error correction means that performs error correction to decode an error correcting code into replacement data, the error correcting code being obtained by a transmission device; and

a descrambling means that descrambles the replacement data,

the transmission device padding control data necessary for demodulation with dummy data,

scrambling post-padding control data that is the padded control data,

generating the replacement data by replacing scrambled dummy data in the scrambled post-padding control data with the dummy data, and

performing error correction encoding on the replacement data.

13. The data processing device according to claim 11, wherein

the transmission device performs shortening by deleting the dummy data from the error correcting code obtained through the error correction encoding and puncturing a parity bit of the error correcting code,

the data processing device further comprising

a restoration means that restores a pre-shortening error correcting code by padding the post-shortening error correcting code obtained by the transmission device with the dummy data, and depuncturing the parity bit.

14. The data processing device according to claim 11, further comprising

a deletion means that deletes descrambled dummy data from the descrambled replacement data.

15. The data processing device according to claim 13, wherein the padding with the dummy data is performed to adjust a data length of padded data to a target data length of the error correction encoding.

16. The data processing device according to claim 13, wherein the scrambling is performed by a scrambling means,

the scrambling means including:

a register group formed with fifteen registers connected in series, a register in a later stage latching bits latched by a register in a previous stage;

a first EXOR circuit that calculates an exclusive OR between bits latched by a fourteenth register and bits latched by a fifteenth register; and

a second EXOR circuit that calculates an exclusive OR between an output of the first EXOR circuit and data to be scrambled, and outputs a result of the calculation as scrambled data,

a first register of the register group latching the output of the first EXOR circuit,

bits 1, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, and 0 being set as initial values in the first through fifteenth registers of the register group, respectively.

17. The data processing device according to claim 13, wherein the control data is one of:

first data necessary for demodulating actual data;

second data necessary for demodulating the first data; and

the first and second data.

18. The data processing device according to claim 13, wherein a new frame containing the error correcting code obtained through the error correction encoding is multiplexed with a T2 frame specified in DVB-T.2 and is transmitted.

19. The data processing device according to claim 13, wherein

a preamble is placed at the top of each of the T2 frame and the new frame,

the preamble of the T2 frame contains information identifying the T2 frame, and

the preamble of the new frame contains information identifying the new frame.

12. A data processing device comprising:

an error correction means that performs error correction to decode an error correcting code into post-padding scrambled data, the error correcting code being obtained by a transmission device;

a deletion means that deletes dummy data from the post-padding scrambled data, and outputs scrambled control data; and

a descrambling means that descrambles the scrambled control data,

the transmission device scrambling control data necessary for demodulation,

padding the scrambled control data with the dummy data, and

performing error correction encoding on the post-padding scrambled data formed by padding the scrambled control data with the dummy data.

20. A data processing method comprising the steps of:

performing error correction to decode an error correcting code into replacement data, the error correcting code being obtained by a transmission device; and

descrambling the replacement data,

the transmission device padding control data necessary for demodulation with dummy data,

scrambling post-padding control data that is the padded control data,

generating the replacement data by replacing scrambled dummy data in the scrambled post-padding control data with the dummy data, and

performing error correction encoding on the replacement data.

21. A data processing method comprising the steps of:

performing error correction to decode an error correcting code into post-padding scrambled data, the error correcting code being obtained by a transmission device;

deleting dummy data from the post-padding scrambled data, to output scrambled control data; and

descrambling the scrambled control data,

the transmission device scrambling control data necessary for demodulation,

padding the scrambled control data with the dummy data, and

performing error correction encoding on the post-padding scrambled data formed by padding the scrambled control data with the dummy data.