INTEGRATED CIRCUIT (IC) HAVING TSVS AND STRESS COMPENSATING LAYER
First Claim
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1. A through-substrate via (TSV) unit cell, comprising:
- a substrate having a topside semiconductor surface and a bottomside surface;
a TSV which extends a full thickness of said substrate comprising an electrically conductive filler material surrounded by a dielectric liner that forms an outer edge for said TSV,a circumscribing region of said topside semiconductor surface surrounding said outer edge of said TSV;
dielectric isolation outside said circumscribing region, anda tensile contact etch stop layer (t-CESL) on said dielectric isolation, and on said circumscribing region.
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Abstract
A through-substrate via (TSV) unit cell includes a substrate having a topside semiconductor surface and a bottomside surface, and a TSV which extends the full thickness of the substrate including an electrically conductive filler material surrounded by a dielectric liner that forms an outer edge for the TSV. A circumscribing region of topside semiconductor surface surrounds the outer edge of the TSV. Dielectric isolation is outside the circumscribing region. A tensile contact etch stop layer (t-CESL) is on the dielectric isolation, and on the circumscribing region.
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Citations
17 Claims
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1. A through-substrate via (TSV) unit cell, comprising:
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a substrate having a topside semiconductor surface and a bottomside surface; a TSV which extends a full thickness of said substrate comprising an electrically conductive filler material surrounded by a dielectric liner that forms an outer edge for said TSV, a circumscribing region of said topside semiconductor surface surrounding said outer edge of said TSV; dielectric isolation outside said circumscribing region, and a tensile contact etch stop layer (t-CESL) on said dielectric isolation, and on said circumscribing region. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An integrated circuit (IC), comprising:
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a substrate having a topside semiconductor surface having active circuitry therein including a plurality of transistors functionally connected by a plurality of metal interconnect levels including a first metal interconnect level and a top metal interconnect level having inter-level dielectric (ILD) layers between respective ones of said plurality of metal interconnect levels, and a bottomside surface; a plurality of through-substrate vias (TSVs) including at least a first TSV which extends from a TSV terminating metal interconnect level selected from said plurality of metal interconnect levels downward to said bottomside surface, said plurality of TSVs comprising an electrically conductive filler material surrounded by a dielectric liner that forms an outer edge for said plurality of TSVs, said first TSV within a TSV unit cell including; a circumscribing region of said topside semiconductor surface surrounding said outer edge; dielectric isolation outside said circumscribing region, and a tensile contact etch stop layer (t-CESL) on said dielectric isolation and on said circumscribing region, and wherein a first metal-oxide-semiconductor (MOS) transistor from said plurality of transistors includes a gate, a source and a drain, wherein at least said source or said drain is positioned proximate said outer edge said first TSV. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14)
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15. A through-substrate via (TSV) unit cell, comprising:
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a substrate having a topside silicon surface and a bottomside surface; a TSV which extends a full thickness of said substrate comprising an copper surrounded by a dielectric liner that forms an outer edge for said TSV, a circumscribing region of said topside silicon surface surrounding said outer edge of said TSV; trench isolation outside said circumscribing region, and a tensile contact etch stop layer (t-CESL) on said trench isolation, on said circumscribing region, and extending to said dielectric liner. - View Dependent Claims (16, 17)
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Specification