INTEGRATED CIRCUIT (IC) HAVING TSVS AND STRESS COMPENSATING LAYER

• US 20130249011A1
• Filed: 06/22/2012
• Published: 09/26/2013
• Est. Priority Date: 03/22/2012
• Status: Abandoned Application

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: WEST, JEFFREY A., CHOI, YOUN SUNG
• Application Number:
  US13/530,744
• Publication Number:
  US 20130249011A1
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A through-substrate via (TSV) unit cell includes a substrate having a topside semiconductor surface and a bottomside surface, and a TSV which extends the full thickness of the substrate including an electrically conductive filler material surrounded by a dielectric liner that forms an outer edge for the TSV. A circumscribing region of topside semiconductor surface surrounds the outer edge of the TSV. Dielectric isolation is outside the circumscribing region. A tensile contact etch stop layer (t-CESL) is on the dielectric isolation, and on the circumscribing region.

Claims

1. A through-substrate via (TSV) unit cell, comprising:

a substrate having a topside semiconductor surface and a bottomside surface;

a TSV which extends a full thickness of said substrate comprising an electrically conductive filler material surrounded by a dielectric liner that forms an outer edge for said TSV,

a circumscribing region of said topside semiconductor surface surrounding said outer edge of said TSV;

dielectric isolation outside said circumscribing region, and

a tensile contact etch stop layer (t-CESL) on said dielectric isolation, and on said circumscribing region.

2. The TSV unit cell of claim 1, wherein said t-CESL extends to said dielectric liner.

3. The TSV unit cell of claim 1, wherein said dielectric isolation comprises trench isolation.

4. The TSV unit cell of claim 1, wherein said filler material comprises copper and said topside semiconductor surface comprises silicon.

5. The TSV unit cell of claim 1, wherein said t-CESL comprises silicon nitride or silicon oxynitride.

6. The TSV unit cell of claim 1, wherein said t-CESL is 20 nm to 80 nm thick.

7. An integrated circuit (IC), comprising:

a substrate having a topside semiconductor surface having active circuitry therein including a plurality of transistors functionally connected by a plurality of metal interconnect levels including a first metal interconnect level and a top metal interconnect level having inter-level dielectric (ILD) layers between respective ones of said plurality of metal interconnect levels, and a bottomside surface;

a plurality of through-substrate vias (TSVs) including at least a first TSV which extends from a TSV terminating metal interconnect level selected from said plurality of metal interconnect levels downward to said bottomside surface, said plurality of TSVs comprising an electrically conductive filler material surrounded by a dielectric liner that forms an outer edge for said plurality of TSVs,

said first TSV within a TSV unit cell including;

a circumscribing region of said topside semiconductor surface surrounding said outer edge;

dielectric isolation outside said circumscribing region, and

a tensile contact etch stop layer (t-CESL) on said dielectric isolation and on said circumscribing region, and

wherein a first metal-oxide-semiconductor (MOS) transistor from said plurality of transistors includes a gate, a source and a drain, wherein at least said source or said drain is positioned proximate said outer edge said first TSV.

8. The IC of claim 7, wherein said t-CESL extends to said dielectric liner.

9. The IC of claim 7, wherein said filler material comprises copper and said topside semiconductor surface comprises silicon.

10. The IC of claim 7, wherein said dielectric isolation comprises shallow trench isolation (STI).

11. The IC of claim 7, wherein said t-CESL comprises silicon nitride or silicon oxynitride.

12. The IC of claim 7, wherein said t-CESL is 20 nm to 80 nm thick.

13. The IC of claim 7, wherein said first MOS transistor comprises an NMOS transistor, and said t-CESL is on said gate, said source and said drain.

14. The IC of claim 13, wherein said plurality of transistors include a PMOS transistor including a gate, a source and a drain, further comprising a compressive CESL on said gate, said source and said drain of said PMOS transistor.

15. A through-substrate via (TSV) unit cell, comprising:

a substrate having a topside silicon surface and a bottomside surface;

a TSV which extends a full thickness of said substrate comprising an copper surrounded by a dielectric liner that forms an outer edge for said TSV,

a circumscribing region of said topside silicon surface surrounding said outer edge of said TSV;

trench isolation outside said circumscribing region, and

a tensile contact etch stop layer (t-CESL) on said trench isolation, on said circumscribing region, and extending to said dielectric liner.

16. The TSV unit cell of claim 15, wherein said t-CESL comprises silicon nitride or silicon oxynitride.

17. The TSV unit cell of claim 16, wherein said t-CESL is 20 nm to 80 nm thick.