Semiconductor Device and Method of Forming a Robust Fan-Out Package including Vertical Interconnects and Mechanical Support Layer

• US 20130249106A1
• Filed: 03/23/2012
• Published: 09/26/2013
• Est. Priority Date: 03/23/2012
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Limited
• Inventors: Lin, Yaojian, Chen, Kang, Gu, Yu
• Granted Patent: US 9,082,780 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49894 Materials of the insulating layers or coatings
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A semiconductor device has a semiconductor die. An encapsulant is deposited around the semiconductor die. An interconnect structure having a conductive bump is formed over the encapsulant and semiconductor die. A mechanical support layer is formed over the interconnect structure and around the conductive bump. The mechanical support layer is formed over a corner of the semiconductor die and over a corner of the interconnect structure. An opening is formed through the encapsulant that extends to the interconnect structure. A conductive material is deposited within the opening to form a conductive through encapsulant via (TEV) that is electrically connected to the interconnect structure. A semiconductor device is mounted to the TEV and over the semiconductor die to form a package-on-package (PoP) device. A warpage balance layer is formed over the encapsulant opposite the interconnect structure.

Claims

1. A method of making a semiconductor device, comprising:

providing a semiconductor die;

depositing an encapsulant around the semiconductor die;

forming an interconnect structure having a conductive bump over the encapsulant and semiconductor die;

forming a mechanical support layer over the interconnect structure and around the conductive bump;

forming an opening through the encapsulant that extends to the interconnect structure; and

depositing conductive material within the opening to form a conductive through encapsulant via (TEV) electrically connected to the interconnect structure.

2. The method of claim 1, further including mounting a semiconductor device to the TEV and over the semiconductor die to form a package-on-package device.

3. The method of claim 2, further including forming flux around the conductive material within the opening.

4. The method of claim 1, further including forming the mechanical support layer over a corner of the semiconductor die and over a corner of the interconnect structure.

5. The method of claim 1, further including forming the mechanical support layer over a first portion of the interconnect structure outside a footprint of the semiconductor die such that a second portion of the interconnect structure within the footprint of the semiconductor die is void of the mechanical support layer.

6. The method of claim 1, further including forming the mechanical support layer partially outside a footprint of the semiconductor die and partially within the footprint of the semiconductor die.

7. A method of making a semiconductor device, comprising:

providing a semiconductor die;

depositing an encapsulant around the semiconductor die;

forming an interconnect structure having a conductive bump over the encapsulant and semiconductor die;

forming a mechanical support layer over the interconnect structure and around the conductive bump; and

forming a through encapsulant via (TEV) through the encapsulant and electrically connected to the interconnect structure.

8. The method of claim 7, wherein forming the TEV further includes:

forming an opening through the encapsulant;

forming a conductive material within the opening; and

forming flux around the conductive material.

9. The method of claim 7, further including forming the mechanical support layer over a corner of the semiconductor die and over a corner of the interconnect structure.

10. The method of claim 7, further including forming the mechanical support layer over a first portion of the interconnect structure outside a footprint of the semiconductor die such that a second portion of the interconnect structure within the footprint of the semiconductor die is void of the mechanical support layer.

11. The method of claim 7, further including forming the mechanical support layer partially outside a footprint of the semiconductor die and partially within the footprint of the semiconductor die.

12. The method of claim 7, wherein forming the interconnect structure includes:

depositing a first insulating layer over the semiconductor die and over the encapsulant;

depositing a conductive layer over the first insulating layer;

depositing a second insulating layer over the conductive layer; and

forming the conductive bump over the second insulating layer and electrically connected to the conductive layer.

13. The method of claim 7, further including forming a warpage balance layer over the encapsulant opposite the interconnect structure.

14. A method of making a semiconductor device, comprising:

providing a semiconductor die;

depositing an encapsulant around the semiconductor die;

forming an interconnect structure over the encapsulant and semiconductor die; and

forming a mechanical support layer over the interconnect structure.

15. The method of claim 14, further including forming a through encapsulant via (TEV) through the encapsulant and electrically connected to the interconnect structure.

16. The method of claim 15, further including mounting a semiconductor device to the TEV and over the semiconductor die to form a package-on-package device.

17. The method of claim 14, further including forming the mechanical support layer over a corner of the semiconductor die and over a corner of the interconnect structure.

18. The method of claim 14, further including forming the mechanical support layer over a first portion of the interconnect structure outside a footprint of the semiconductor die such that a second portion of the interconnect structure within the footprint of the semiconductor die is void of the mechanical support layer.

19. The method of claim 14, further including forming the mechanical support layer partially outside a footprint of the semiconductor die and partially within the footprint of the semiconductor die.

20. The method of claim 14, wherein forming the interconnect structure includes:

depositing a first insulating layer over the semiconductor die and over the encapsulant;

depositing a conductive layer over the first insulating layer;

depositing a second insulating layer over the conductive layer; and

forming a conductive bump over the second insulating layer and electrically connected to the conductive layer.

21. A semiconductor device, comprising:

a semiconductor die;

an encapsulant deposited around the semiconductor die;

an interconnect structure formed over the encapsulant and semiconductor die;

a mechanical support layer formed over the interconnect structure; and

a through encapsulant via (TEV) formed through the encapsulant and electrically connected to the interconnect structure.

22. The semiconductor device of claim 21, wherein the mechanical support layer is formed over a corner of the semiconductor die and over a corner of the interconnect structure.

23. The semiconductor device of claim 21, wherein the mechanical support layer is formed over a first portion of the interconnect structure outside a footprint of the semiconductor die and a second portion of the interconnect structure within the footprint of the semiconductor die is void of the mechanical support layer.

24. The semiconductor device of claim 21, wherein the mechanical support layer is formed partially outside a footprint of the semiconductor die and partially within the footprint of the semiconductor die.

25. The semiconductor device of claim 21, further including a warpage balance layer formed over the encapsulant opposite the interconnect structure.