CONSTANT VOLTAGE CONSTANT CURRENT CONTROL CIRCUITS AND METHODS WITH IMPROVED LOAD REGULATION

• US 20130250629A1
• Filed: 02/28/2013
• Published: 09/26/2013
• Est. Priority Date: 03/26/2012
• Status: Active Grant

• Current Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd. (Silergy Corporation)
• Original Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd. (Silergy Corporation)
• Inventors: Xu, Xiaoru
• Granted Patent: US 8,913,404 B2
• Time in Patent Office: Days
• US Class Current: 363/21.17
• CPC Class Codes: H02M 1/0032 Control circuits allowing low power mode operation, e.g. in standby mode
• CPC Class Codes: H02M 3/33507 with automatic control of the output voltage or current, e.g. flyback converters H02M3/33561, H02M3/33569 take precedence
• CPC Class Codes: H02M 3/33523 with galvanic isolation between input and output of both the power stage and the feedback loop
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The present invention discloses CVCC circuits and methods with improved load regulation for an SMPS. In one embodiment, the CVCC can include: a voltage feedback circuit to generate an output voltage feedback signal; a current feedback circuit to generate an output current feedback signal; a control signal generating circuit that receives the output voltage feedback signal and the output current feedback signal, and generates a constant voltage/constant current control signal; a first enable signal generating circuit that compares a first reference voltage and the constant voltage/constant current control signal to generate a first enable signal; and a PWM controller that generates a PWM control signal based on the constant voltage/constant current control signal to control a main switch of the flyback SMPS.

Claims

1. A constant voltage constant current (CVCC) control circuit for load regulation for a flyback switch mode power supply (SMPS), the CVCC comprising:

a) a voltage feedback circuit configured to generate an output voltage feedback signal;

b) a current feedback circuit configured to generate an output current feedback signal;

c) a control signal generating circuit configured to receive said output voltage feedback signal and said output current feedback signal, and to generate a constant voltage/constant current control signal;

d) a first enable signal generating circuit configured to compare a first reference voltage and said constant voltage/constant current control signal to generate a first enable signal; and

e) a pulse-width modulation (PWM) controller configured to generate a PWM control signal based on said constant voltage/constant current control signal to control a main switch of said flyback SMPS, wherein said PWM control signal is configured to turn on said main switch when said first enable signal is inactive, and wherein said main switch remains off when said first enable signal is active.

2. The CVCC control circuit of claim 1, wherein, said control signal generating module comprises:

a) a current controller configured to calculate a difference between said output current feedback signal and a first reference current to generate an error signal;

b) a voltage controller configured to compare said output voltage feedback signal against a second reference voltage to generate a first control signal; and

c) a select controller configured to control whether said flyback SMPS operates in a constant voltage mode or a constant current mode based on said first control signal and said error signal, and to generate said constant voltage/constant current control signal.

3. The CVCC control circuit of claim 1, wherein said first enable signal generating module comprises a first hysteresis comparator having a non-inverting input terminal configured to receive said first reference voltage, an inverting input terminal configured to receive said constant voltage/constant current control signal, and an output terminal configured to output said first enable signal.

4. The CVCC control circuit of claim 2, wherein said voltage controller comprises:

a) a first comparator having a non-inverting input terminal configured to receive said second reference voltage, an inverting input terminal configured to receive said output voltage feedback signal, and an output terminal configured to output a middle signal; and

b) a first logic controller configured to receive said middle signal, and to generate said first control signal, wherein said PWM control signal is used as a clock signal for said first logic controller.

5. The CVCC control circuit of claim 2, wherein said select controller comprises:

a) an OR-gate configured to receive said first control signal and said first enable signal;

b) a first switch, wherein a control terminal of said first switch is coupled to an output terminal of said first OR-gate, and a first terminal of said first switch is configured to receive said error signal;

c) a second switch coupled to said first switch and a discharge circuit, wherein said second switch is configured to turn on when said first enable signal and said first control signal are inactive; and

d) a capacitor coupled to ground and a common junction of said first switch and said second switch, wherein a voltage across said first capacitor is configured as said constant voltage/constant current control signal.

6. The CVCC control circuit of claim 1, further comprising a second enable signal generating module having:

a) a second comparator configured to receive said output voltage feedback signal and a third reference voltage;

b) a first AND-gate coupled to receive an output of said second comparator and an inverted version of said PWM control signal; and

c) an RS flip-flop, wherein a reset terminal of said RS flip-flop is coupled to an output of said first AND-gate, a set terminal of said RS flip-flop is coupled to said first enable signal, and an output terminal of said RS flip-flop is configured to output a second enable signal,

d) wherein said PWM control signal is configured to turn on said main switch when said second enable signal is active and said first enable signal is inactive, and

e) wherein said main switch remains off when said second enable signal is inactive or said first enable signal is active.

7. The CVCC control circuit of claim 6, further comprising:

a) a second AND-gate configured to receive said first control signal and said second enable signal, and having an output coupled to said control signal generating module; and

b) a recovery circuit configured to pull down said output voltage feedback signal to fast recover an output of said second comparator to a low level when said output of said second comparator is active.

8. A constant voltage constant current (CVCC) control method for load regulation for a flyback switch mode power supply (SMPS), the method comprising:

a) obtaining an output current feedback signal and an output voltage feedback signal;

b) generating a constant voltage/constant current control signal based on said output current feedback signal and said output voltage feedback signal;

c) generating a first enable signal based on said constant voltage/constant current control signal and a first reference voltage;

d) controlling a main switch of said flyback SMPS based on said first enable signal, wherein said main switch is turned off by said first enable signal when said first enable signal is active;

e) generating, in a first operation mode, a pulse-width modulation (PWM) control signal based on said constant current control signal to control said main switch to maintain substantially constant output current; and

f) generating, in a second operation mode, said PWM control signal based on said constant voltage control signal, wherein said PWM control signal is used to control said main switch when said first enable signal is inactive.

9. The method of claim 8, further comprising:

a) generating an error signal by calculating a difference between said output current feedback signal and a first reference current;

b) comparing said output voltage feedback signal against a second reference voltage to generate said first control signal; and

c) selecting one of said first and second operation modes of said flyback SMPS based on said error signal and said first control signal.

10. The method of claim 8, further comprising:

a) obtaining a second enable signal based on said output voltage feedback signal, a third reference voltage, said PWM control signal, and said first enable signal;

b) controlling said main switch based on said PWM control signal when said second enable signal is active and said first enable signal is inactive; and

c) turning off said main switch when said second enable signal is inactive or said first enable signal is active.