Semiconductor Memory Having Both Volatile and Non-Volatile Functionality and Method of Operating
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Abstract
Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.
152 Citations
39 Claims
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1-22. -22. (canceled)
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23. A semiconductor memory device comprising a string of memory cells connected in series, each said memory cell having:
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a floating body region configured to be charged to a level indicative of a state of said memory cell to store the state as volatile memory; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a floating gate or trapping layer positioned between said first and second regions and configured to receive transfer of data stored as said volatile memory and store said data as non-volatile memory indicative of said state of the memory cell; and a control gate positioned above said floating gate or trapping layer, wherein said charge stored in said floating body region determines a charge stored in said floating gate or trapping layer upon interruption of power to said semiconductor memory device. - View Dependent Claims (24, 25, 26, 27)
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28. A semiconductor memory device comprising a string of memory cells connected in series, each said memory cell having:
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a floating body region configured to be charged to a level indicative of a state of said memory cell to store the state as volatile memory; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a floating gate or trapping layer positioned between said first and second regions and configured to receive transfer of data stored as said volatile memory and store said data as nonvolatile memory indicative of said state of the memory cell; and a control gate positioned above the floating gate or trapping layer, wherein said state stored in said floating body region determines a current flowing through said semiconductor memory cell. - View Dependent Claims (29, 30, 31, 32, 33)
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34. A semiconductor memory device comprising a string of memory cells connected in series, each said memory cell having:
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a floating body region; and a floating gate or trapping layer positioned above and insulated from said floating body region; wherein said floating body region is configured to be charged to a level indicative of a state of said memory cell based on charge stored in said floating gate or trapping layer, upon restoration of power to said semiconductor memory device. - View Dependent Claims (35, 36, 37, 38, 39)
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Specification