SHARED-BIT-LINE BIT LINE SETUP SCHEME
First Claim
1. A non-volatile storage system, comprising:
- a first NAND string in communication with a shared bit line, the first NAND string includes a first channel;
a second NAND string in communication with the shared bit line, the second NAND string includes a second channel; and
one or more managing circuits in communication with the first NAND string and the second NAND string, the one or more managing circuits precharge the first channel to a first voltage at a first point in time, the precharging of the first channel boosts the second channel to a first boosted voltage less than the first voltage, the one or more managing circuits precharge the second channel to the first voltage at a second point in time subsequent to the first point in time, the precharging of the second channel boosts the first channel to a second voltage greater than the first voltage, the one or more managing circuits set the shared bit line to a programming voltage at a third point in time subsequent to the second point in time.
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Accused Products
Abstract
Methods for operating a non-volatile storage system utilizing a shared-bit-line NAND architecture are described. A shared-bit-line NAND architecture includes one or more pairs of NAND strings, wherein each pair of the one or more pairs of NAND strings shares a common bit line. In some embodiments, a pair of NAND strings includes an odd NAND string adjacent to an even NAND string. Prior to programming a memory cell associated with the even NAND string, an odd channel associated with the odd NAND string (i.e., the NAND string of the pair that is not selected for programming) is precharged to a bit line inhibit voltage, floated, and then boosted to a second voltage greater than the bit line inhibit voltage as an even channel associated with the even NAND string is precharged. Subsequently, the odd channel may be boosted (e.g., via self-boosting) prior to programming the memory cell.
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Citations
20 Claims
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1. A non-volatile storage system, comprising:
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a first NAND string in communication with a shared bit line, the first NAND string includes a first channel; a second NAND string in communication with the shared bit line, the second NAND string includes a second channel; and one or more managing circuits in communication with the first NAND string and the second NAND string, the one or more managing circuits precharge the first channel to a first voltage at a first point in time, the precharging of the first channel boosts the second channel to a first boosted voltage less than the first voltage, the one or more managing circuits precharge the second channel to the first voltage at a second point in time subsequent to the first point in time, the precharging of the second channel boosts the first channel to a second voltage greater than the first voltage, the one or more managing circuits set the shared bit line to a programming voltage at a third point in time subsequent to the second point in time. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method for operating a non-volatile storage system, comprising:
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applying a first voltage to a first channel associated with a first NAND string; applying a second voltage to a second channel associated with a second NAND string subsequent to the applying a first voltage, the second NAND string is adjacent to the first NAND string, the second NAND string and the first NAND string share a common bit line, the applying a first voltage boosts the second channel to a first boosted voltage less than the first voltage, the applying a second voltage boosts the first channel to a second boosted voltage greater than the first voltage; setting the common bit line to a programming voltage subsequent to the applying a second voltage; boosting the first NAND string and the second NAND string subsequent to the setting the common bit line; and programming a storage element of the second NAND string subsequent to the boosting the first NAND string and the second NAND string. - View Dependent Claims (14, 15, 16, 17)
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18. A non-volatile storage system, comprising:
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a first bit line; a plurality of word lines; a first selection line; a second selection line; a first NAND string in communication with the first bit line, the first NAND string includes a first plurality of non-volatile storage elements and a first selection gate, the first NAND string includes a first channel; and a second NAND string in communication with the first bit line, the second NAND string includes a second plurality of non-volatile storage elements and a second selection gate, the second NAND string includes a second channel, the plurality of word lines are in communication with the first NAND string and the second NAND string, the first selection line is connected to the first selection gate, the second selection line is connected to the second selection gate, the first channel is set to a first voltage at a first point in time, the second channel is set to the first voltage at a second point in time subsequent to the first point in time, the setting of the second channel to the first voltage boosts the first channel to a second voltage greater than the first voltage, the first bit line is biased to a bit line programming voltage at a third point in time subsequent to the second point in time. - View Dependent Claims (19, 20)
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Specification