Adaptive Programming For Non-Volatile Memory Devices

• US 20130250692A1
• Filed: 03/20/2012
• Published: 09/26/2013
• Est. Priority Date: 03/20/2012
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Manea, Danut, Castillon, Erwin, Mudumba, Uday, Trinh, Stephen, Nguyen, Dixie, Centazzo, Sabina
• Granted Patent: US 8,885,413 B2
• Time in Patent Office: Days
• US Class Current: 365/185.18
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

Systems and techniques for performing write operations on non-volatile memory are described. A described system includes a memory structure including non-volatile memory cells that are arranged on word lines and bit lines and a microcontroller that is communicatively coupled with the memory structure. The memory structure can include non-volatile memory cells that are arranged on word lines and bit lines. The microcontroller can be configured to receive data to write to the memory structure, write the data to the memory structure using a selected word line of the word lines, detect a failure to write the data, apply, based on the failure, a negative bias voltage to one or more unselected word lines of the word lines during a negative bias period, and write the data to the portion of the memory cells using the selected word line during the negative bias period.

Claims

1. An apparatus comprising:

a memory structure comprising non-volatile memory cells that are arranged on word lines and bit lines; and

a microcontroller that is communicatively coupled with the memory structure, the microcontroller configured to receive data to write to the memory structure, write the data to the memory structure using a selected word line of the word lines, detect a failure to write the data, apply, based on the failure, a negative bias voltage to one or more unselected word lines of the word lines during a negative bias period, and write the data to the portion of the memory cells using the selected word line during the negative bias period.

2. The apparatus of claim 1, wherein the failure is based on two or more mismatches between the data and two or more read back versions of the data corresponding to two or more attempts to write the data to the memory structure.

3. The apparatus of claim 2, wherein the microcontroller is configured to apply a first voltage to the selected word lines for the two or more attempts and apply a second voltage to the one or more unselected word lines for the two or more attempts, wherein the second voltage is less than the first voltage, and wherein the negative bias voltage is less than the second voltage.

4. The apparatus of claim 3, wherein the second voltage is a ground voltage.

5. The apparatus of claim 1, wherein the microcontroller is configured to send a failure indication to a component responsible for providing the data to the microcontroller based on a failure to write the data to the memory structure using the selected word line during the negative bias period.

6. The apparatus of claim 1, wherein the negative bias voltage is equal to or less than −

0.5 volts and is not less than −

3 volts.

7. The apparatus of claim 1, wherein the memory cells are flash memory cells.

8. The apparatus of claim 1, wherein the memory structure and the microcontroller are integrated on a single integrated circuit.

9. A system comprising:

a memory module comprising a microcontroller and non-volatile memory cells that are arranged on word lines and bit lines; and

a memory controller that is communicatively coupled with the memory structure, the memory controller configured to provide data to the memory module for storage,

wherein the microcontroller is configured to write the data to the a portion of the memory cells using a selected word line of the word lines, detect a failure to write the data, apply, based on the failure, a negative bias voltage to one or more unselected word lines of the word lines, and write the data to the memory structure using the selected word line while the negative bias voltage is applied to the one or more unselected word lines.

10. The system of claim 9, wherein the failure is based on two or more mismatches between the data and two or more read back versions of the data corresponding to two or more attempts to write the data to the memory structure.

11. The system of claim 10, wherein the microcontroller is configured to apply a first voltage to the selected word lines for the two or more attempts and apply a second voltage to the one or more unselected word lines for the two or more attempts, wherein the second voltage is less than the first voltage, and wherein the negative bias voltage is less than the second voltage.

12. The system of claim 11, wherein the second voltage is a ground voltage.

13. The system of claim 9, wherein the microcontroller is configured to send a failure indication to the memory controller based on a failure to write the data to the memory structure using the selected word line while the negative bias voltage is applied to the one or more unselected word lines.

14. The system of claim 9, wherein the memory cells are flash memory cells.

15. The system of claim 9, wherein the memory controller provides a memory address to the microcontroller, wherein the selected word line is selected by the microcontroller based on the memory address, and wherein the one or more unselected word lines are the remaining ones of the word lines that are not selected based on the memory address.

16. A method comprising:

receiving data to write to a memory structure, the memory structure comprising non-volatile memory cells that are arranged on word lines and bit lines;

writing the data to the memory structure using a selected word line of the word lines;

detecting a failure to write the data;

applying, based on the failure, a negative bias voltage to one or more unselected word lines of the word lines during a negative bias period; and

writing, during the negative bias period, the data to the memory structure using the selected word line.

17. The method of claim 16, wherein detecting the failure comprises detecting two or more mismatches between the data and two or more read back versions of the data corresponding to two or more attempts to write the data to the memory structure.

18. The method of claim 17, further comprising:

applying, for the two or more attempts, a first voltage to the selected word line; and

applying, for the two or more attempts, a second voltage to the one or more unselected word lines, wherein the second voltage is less than the first voltage, wherein the negative bias voltage is less than the second voltage.

19. The method of claim 18, wherein the second voltage is a ground voltage.

20. The method of claim 16, further comprising:

detecting an additional failure to write the data while applying the negative bias voltage to the one or more unselected word lines; and

providing, based on the additional failure, a failure indication to a component responsible for providing the data.