SEMICONDUCTOR MEMORY AND VOLTAGE OUTPUT MEASURING METHOD OF THE SEMICONDUCTOR MEMORY

• US 20130250702A1
• Filed: 09/07/2012
• Published: 09/26/2013
• Est. Priority Date: 03/23/2012
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: IWATA, Yoshihisa, SAKURAI, Katsuaki
• Granted Patent: US 9,293,175 B2
• Time in Patent Office: Days
• US Class Current: 365/189.09
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

A semiconductor memory device includes a first comparative device, to which first and second voltages are input; a first capacitor, which accumulates the electrical potential of a first node; a power source, which outputs the first electric current to a second node; a resistor, which generates a third voltage in the second node; a second capacitor, which accumulates the electric potential of the second node; first switches, which make a common connection at a third node possible for the first node and the second node, to which the first capacitor and the second capacitor are connected respectively; and a second comparison device, which uses as an input voltage a fourth voltage, which is obtained as a result of the charge share between the first and the second capacitors and the electrical potential of a fourth node, and equalizes the electrical potential of the fourth node with the fourth voltage.

Claims

1. A voltage generator for a semiconductor memory device, comprising:

a first voltage generator circuit for generating a selected source line voltage; and

a second voltage generator circuit for generating an unselected source line voltage, the second voltage generator circuit including a reference current generator, a transistor connected between a reference voltage and an output node from which output voltage is supplied to the unselected source line, a resistor connected between the output node and the reference current generator, and a comparator that compares the selected source line voltage and a voltage at a monitored node between the resistor and the reference current generator and outputting a gate signal for the transistor.

2. The voltage generator according to claim 1, wherein the comparator causes the transistor to turn ON when the selected source line voltage is greater than the voltage at the monitored node.

3. The voltage generator according to claim 2, wherein the comparator causes the transistor to turn OFF when the selected source line voltage is less than the voltage at the monitored node.

4. The voltage generator according to claim 3, wherein output voltage of the comparator is less when turning the transistor ON than when turning the transistor OFF.

5. The voltage generator according to claim 4, wherein the output voltage of the comparator is greater than zero when turning the transistor ON.

6. The voltage generator according to claim 1, wherein the transistor is an n-channel type MOS transistor.

7. The voltage generator according to claim 6, wherein the current source is configured to generate a current having a magnitude that is independent of thermal conditions.

8. The voltage generator according to claim 1, wherein the current source comprises a supplementary transistor disposed to form a miller circuit with the transistor.

9. A semiconductor memory having a voltage generator, the voltage generator comprising:

a first comparison device configured to have a first voltage input thereto, compare the first voltage with a second voltage at a first node, and to output a comparison result that causes the second voltage at the first node to be equal to the first voltage;

a first capacitor connected between ground and a second node;

a first switch configured to electrically connect and disconnect the first and second nodes;

a current source configured to output a current to a third node;

a first resistor connected between ground and the third node;

a second capacitor connected between ground and a fourth node;

a second switch configured to electrically connect and disconnect the third and fourth nodes;

a third switch configured to electrically connect and disconnect the first node and a fifth node, and a fourth switch configured to electrically connect and disconnect the fourth node and the fifth node; and

a second comparison device configured to have a third voltage input thereto, compare the third voltage with a fourth voltage, and to output an output voltage, wherein the third voltage is a voltage at the fifth node and the fourth voltage is a percentage of the output voltage.

10. The semiconductor memory of claim 9, further comprising a transistor having a gate to which the comparison result of the first comparison device is supplied.

11. The semiconductor memory of claim 10, wherein the transistor turns ON when the second voltage is higher than the first voltage, and turns OFF when the second voltage is lower than the first voltage.

12. The semiconductor memory of claim 11, wherein the transistor is an n-channel type MOS transistor.

13. The semiconductor memory of claim 9, wherein the current source comprises:

a third comparison device configured to compare a reference voltage with a fourth voltage input thereto, and output a third comparison device output voltage that affects the fourth voltage;

a transistor configured to be turned ON or OFF by the third comparison device output voltage;

a resistor; and

a miller circuit having a group of transistors and configured to generate a current through one of the transistors,

wherein the current generated through one of the transistors is the current that is output to the third node.

14. A semiconductor memory comprising a voltage generator circuit, the voltage generator circuit comprising:

a comparison device configured to compare a first voltage with a second voltage at a first node;

a first transistor with one end connected to the first node, the first transistor configured to be turned ON or OFF by an output of the comparison device;

a current source configured to output a current to a second node;

a first resistor connected between the first and second nodes; and

a supplementary transistor disposed to form a miller circuit with the first transistor, and configured to provide a supplemental electric current at the first node, the supplemental current being generated based on the output of the comparison device.

15. The semiconductor memory of claim 14, wherein the comparator causes the first transistor to turn ON when the first voltage is greater than the second voltage.

16. The semiconductor memory of claim 15, wherein the comparator causes the first transistor to turn OFF when the first voltage is less than the second voltage.

17. The semiconductor memory of claim 16, wherein the first transistor is an n-channel type MOS transistor.

18. The semiconductor memory of claim 15, wherein the current source is configured to generate a current having a magnitude that is independent of thermal conditions.

19. The semiconductor memory of claim 14, wherein the current source comprises multiple sets of series connected transistors.

20. The semiconductor memory of claim 14, wherein the current source is configured with a Miller circuit.