MULTI-MODE POWER AMPLIFIER ARCHITECTURE

• US 20130250820A1
• Filed: 05/06/2013
• Published: 09/26/2013
• Est. Priority Date: 10/07/2009
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Khlat, Nadim
• Granted Patent: US 9,319,214 B2
• Time in Patent Office: Days
• US Class Current: 370/280
• CPC Class Codes: H04B 1/0057 using diplexing or multiplexing filters for selecting the desired band
• CPC Class Codes: H04L 5/14 Two-way operation using the same type of signal, i.e. duplex
• CPC Class Codes: H04L 5/18 Automatic changing of the traffic direction

Abstract

Radio frequency (RF) circuitry, which includes a time division duplex (TDD)/frequency division duplex (FDD) driver stage, a TDD final stage, an FDD final stage, and power directing circuitry, is disclosed. The power directing circuitry is coupled between the TDD/FDD driver stage and the TDD final stage, and is further coupled between the TDD/FDD driver stage and the FDD final stage.

Claims

1. Radio frequency (RF) circuitry comprising:

a time division duplex (TDD)/frequency division duplex (FDD) driver stage;

a TDD final stage;

an FDD final stage; and

power directing circuitry coupled between the TDD/FDD driver stage and the TDD final stage, and further coupled between the TDD/FDD driver stage and the FDD final stage.

2. The RF circuitry of claim 1 further comprising RF bypass circuitry coupled to an output from the TDD/FDD driver stage.

3. The RF circuitry of claim 2 adapted to operate in one of a TDD operating mode, an FDD operating mode, and a bypass operating mode, such that:

during the TDD operating mode, the TDD final stage is adapted to provide a first RF output signal;

during the FDD operating mode, the FDD final stage is adapted to provide a second RF output signal; and

during the bypass operating mode, the TDD/FDD driver stage is adapted to provide a third RF output signal.

4. The RF circuitry of claim 3 wherein:

during the TDD operating mode, the FDD final stage is further adapted to be disabled;

during the FDD operating mode, the TDD final stage is further adapted to be disabled; and

during the bypass operating mode, both the TDD final stage and the FDD final stage are further adapted to be disabled.

5. The RF circuitry of claim 1 wherein:

the TDD final stage is a single-ended stage; and

the FDD final stage is a quadrature stage comprising an in-phase stage and a quadrature-phase stage.

6. The RF circuitry of claim 5 wherein:

the power directing circuitry comprises a 90 degree power splitter;

an in-phase port from the 90 degree power splitter is coupled to the in-phase stage;

a quadrature-phase port from the 90 degree power splitter is coupled to the quadrature-phase stage; and

an isolated port from the 90 degree power splitter is coupled to the TDD final stage.

7. The RF circuitry of claim 1 wherein the power directing circuitry comprises an RF power splitter.

8. The RF circuitry of claim 1 wherein the power directing circuitry comprises an RF multiplexer.

9. The RF circuitry of claim 1 wherein the power directing circuitry comprises an RF switch.

10. The RF circuitry of claim 1 further comprising a direct current (DC)-DC converter coupled between a DC power source and the FDD final stage.

11. The RF circuitry of claim 10 further comprising the DC power source.

12. The RF circuitry of claim 10 wherein the DC power source is a battery.

13. The RF circuitry of claim 10 wherein:

the TDD/FDD driver stage is coupled to the DC-DC converter; and

the TDD final stage is coupled to the DC power source.

14. The RF circuitry of claim 1 adapted to operate in one of a TDD operating mode and an FDD operating mode, such that:

during the TDD operating mode, the TDD final stage is adapted to provide a first RF output signal;

during the FDD operating mode, the FDD final stage is adapted to provide a second RF output signal; and

during both the TDD operating mode and the FDD operating mode, the TDD/FDD driver stage is adapted to provide a driver stage output signal.

15. The RF circuitry of claim 14 wherein the FDD operating mode comprises a first FDD operating mode and a second FDD operating mode.

16. The RF circuitry of claim 14 wherein control circuitry is adapted to select the one of the TDD operating mode and the FDD operating mode.

17. The RF circuitry of claim 16 further comprising the control circuitry.

18. The RF circuitry of claim 14 wherein the second RF output signal is a long term evolution (LTE) RF signal.

19. The RF circuitry of claim 14 wherein the second RF output signal is a wideband code division multiple access (WCDMA) RF signal.

20. The RF circuitry of claim 14 wherein the first RF output signal is a global system for mobile communications (GSM) RF signal.

21. The RF circuitry of claim 14 wherein the first RF output signal is a long term evolution (LTE) RF signal.

22. The RF circuitry of claim 14 wherein the first RF output signal is a time division synchronous code division multiple access (TD-SCDMA) RF signal.

23. A method comprising:

during both a time division duplex (TDD) operating mode and a frequency division duplex (FDD) operating mode, providing a driver stage output signal via a TDD/FDD driver stage;

during the TDD operating mode, directing the driver stage output signal to a TDD final stage;

during the FDD operating mode, directing the driver stage output signal to an FDD final stage;

during the TDD operating mode, providing a first RF output signal via the TDD final stage; and

during the FDD operating mode, providing a second RF output signal via the FDD final stage.