MULTI-RATE FILTER AND FILTERING METHOD FOR DIGITAL PRE-DISTORTERS

• US 20130251065A1
• Filed: 06/21/2012
• Published: 09/26/2013
• Est. Priority Date: 03/22/2012
• Status: Active Grant

• Current Assignee: DBEZ Firenze LLC (SoftBank Group Corp.)
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: BAI, Chunlong
• Granted Patent: US 8,731,105 B2
• Time in Patent Office: Days
• US Class Current: 375/296
• CPC Class Codes: H03F 1/3241 using predistortion circuits H03F1/3211, H03F1/3217 take precedence
• CPC Class Codes: H03F 1/3247 using feedback acting on predistortion circuits H03F1/3264 takes precedence
• CPC Class Codes: H04B 1/0475 with means for limiting noise, interference or distortion H04B1/0483 takes precedence
• CPC Class Codes: H04B 2001/0425 with linearisation using predistortion

Abstract

A method and apparatus for modeling distortion of a non-linear device are disclosed. A pre-distorter model has a plurality of branches. Each branch receives a different output basis function signal. At least one branch includes a down-sampler, a memory structure and an up-sampler. The down-sampler down-samples the received output basis function signal received by the branch by a factor of 1/M_k, where M_k is different for each of the at least one branches. The memory structure includes at least one delay element to delay the output of the down-sampler according to a predetermined delay. The memory structure has an output based on an output of the at least one delay element. The up-sampler up-samples the output of the memory structure by the up-sampling factor, M_k.

Claims

1. A pre-distorter memory modeling apparatus, comprising:

a plurality of branches, each branch receiving a different output basis function signal, at least one branch including;

a down-sampler, the down-sampler down-sampling the received output basis function signal received at the branch by a down-sampling factor of 1/M_k, M_k being different for each of the at least one branch; and

a memory structure, the memory structure receiving and filtering an output of the down-sampler, the memory structure including;

at least one delay element, at least one of the at least one delay element delaying the output of the down-sampler according to a corresponding pre-determined delay; and

a memory structure output based on an output of the at least one delay element; and

an up-sampler, the up-sampler up-sampling the memory structure output by an up-sampling factor equal to M_k.

2. The apparatus of claim 1, wherein the down-sampler includes an accumulator and a register, the accumulator and register cooperatively configured to low-pass filter and down-sample the received output basis function signal.

3. The apparatus of claim 1, wherein the up-sampler includes an interpolator configured to interpolate over M_k−

1 zeros between non-zero samples.

4. The apparatus of claim 1, wherein the pre-determined delay is different for each branch.

5. The apparatus of claim 1, wherein the factor M_k of a branch of the plurality of branches is based on an evaluation period associated with the corresponding branch.

6. The apparatus of claim 5, wherein an evaluation period associated with a first branch of the plurality of branches is on an order of nanoseconds and an evaluation period associated with a second branch of the plurality of branches is on an order of microseconds.

7. The apparatus of claim 5, wherein an evaluation period associated with a first branch of the plurality of branches is on an order of microseconds and an evaluation period associated with a second branch of the plurality of branches is on and order of milliseconds.

8. The apparatus of claim 1, wherein the factor M_k is related to a number of delay elements in the memory structure of a corresponding branch of the plurality of branches.

9. The apparatus of claim 8, wherein an increase in a number of delay elements of the memory structure of a branch of the plurality of branches is associated with a decrease in the corresponding factor M_k of the branch of the plurality of branches.

10. The apparatus of claim 1, wherein the factor M_k is based on an exponential power associated with the output basis function signal received at the corresponding branch of the plurality of branches.

11. The apparatus of claim 10, wherein an increase in the exponential power associated with the output basis function is associated with a decrease in the factor M_k of the corresponding branch of the plurality of branches.

12. A method of calculating a distortion signal, d(n), comprising:

receiving an input signal, x(n);

supplying the input signal, x(n), to each of K branches, where K is an integer not less than 1;

in each of the K branches, operating on the input signal, x(n), by a different basis function, to produce in each branch an output signal, u_k(n), where k=0 to K−

1; and

in each of the K branches, applying one of the K output signals, u_k(n), to a different one of K memory models, each of the K memory models;

down-sampling the signal u_k(n) by a factor 1/M_k, to produce a down-sampled signal, v_k(n);

filtering the down-sampled signal v_k(n) by a filter including at least one delay element to produce a filtered output;

up-sampling the filtered output by the factor, M_k, to produce a distortion component d_k(n); and

adding the outputs d_k(n) of each branch to produce the distortion signal d(n).

13. The method of claim 12, wherein operating on the input signal by a basis function includes raising the input signal x(n) by an integer power, the integer denoting the order of the basis function.

14. The method of claim 12, wherein the factor M_k of a branch of the K branches is related to the order of the basis function.

15. The method of claim 12, wherein an amount of delay of a delay element is associated with an order of the basis function.

16. The method of claim 12, wherein the factor M_k of a branch of the K branches is based on an evaluation period associated with the branch.

17. The method of claim 16, wherein an amount of delay provided by the filter is related to the factor M_k of the corresponding branch.

18. A pre-distorter memory module, comprising:

a combination of a register and an accumulator, the combination arranged to low-pass filter and down-sample an input signal;

a filter comprising at least one delay element, the filter producing a filtered output;

an interpolator, comprising;

a first delay element receiving the filtered output and producing a first delay element output;

a first multiplier, the first multiplier multiplying the first delay element output by a first factor;

a second delay element receiving the first delay element output and producing a second delay element output;

a second multiplier, the second multiplier multiplying the second delay element output by a second factor; and

an adder, the adder adding the output of the first multiplier and the second multiplier.

19. The pre-distorter of claim 18, wherein the second factor is one minus the first factor.

20. The pre-distorter of claim 18, wherein the first and second delay elements operate at a down-sampled rate of an output of the register.