CONTROLLING A PROCESSOR CACHE USING A REAL-TIME ATTRIBUTE

• US 20130254491A1
• Filed: 12/22/2011
• Published: 09/26/2013
• Est. Priority Date: 12/22/2011
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Coleman, James A., Srivastava, Durgesh
• Application Number:
  US13/993,052
• Publication Number:
  US 20130254491A1
• Time in Patent Office: Days
• US Class Current: 711/133
• CPC Class Codes: G06F 12/123 with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 2212/70 Details relating to dynamic memory management

Abstract

A processor device has a cache, and a cache controller that manages the replacement of a number of cache lines in the cache, in accordance with a replacement policy. A storage location is to be configured to define a memory map having a cacheable region, an un-cacheable region, and a real time region. Upon a cache miss of an address that lies in the real time region, the cache controller responds by loading content at the address into a cache line, and then prevents the cache line from aging as would a cache line that is in the cacheable region. Other embodiments are also described and claimed.

Claims

1. A processor device comprising:

a cache;

a cache controller coupled to the cache to manage the replacement of a plurality of cache lines in the cache, in accordance with a replacement policy in which each of the cache lines has an associated age indicator; and

a storage location that is to be configured to define a memory map having a cacheable region, an un-cacheable region, and a real time region, wherein upon a cache miss of an address that lies in the real time region, the cache controller is to respond by loading content at said address into a cache line and then prevent the cache line from aging as would a cache line that is in the cacheable region.

2. The processor device of claim 1 wherein the storage location comprises a register that defines the memory map in physical address space.

3. The processor device of claim 1 wherein the storage location is to be configured to define the cacheable region as one of the group consisting of:

write through, write combine, write protect, and write back.

4. The processor device of claim 1 wherein the storage location comprises a plurality of entries, each entry having an address range, an associated cacheable/un-cacheable attribute, and an associated real time attribute.

5. The processor device of claim 3 wherein the storage location comprises a plurality of entries, each entry having an address range, an associated cacheable/un-cacheable attribute, and an associated real time attribute.

6. The processor device of claim 4 wherein the cache controller comprises increment age logic that has an output which indicates that the associated age indicator of a cache line is to be incremented, in accordance with the replacement policy, and wherein the output of the increment age logic is qualified by the associated real time attribute.

7. The processor device of claim 4 wherein for each entry in the storage location, the real time attribute comprises a plurality of bits which can indicate any one of the group consisting of:

ageless, low rate aging, and high rate aging.

8. The processor device of claim 4 wherein the associated real time attribute indicates one of slow aging and normal aging.

9. The processor device of claim 6 wherein the associated real time attribute indicates one of slow aging and normal aging.

10. A method for controlling a processor cache, comprising:

receiving a request for content at a memory address, and in response accessing a processor cache that has a replacement policy, to generate one of a cache hit and a cache miss for the memory address;

in response to the cache miss, loading content at the memory address into a cache line;

performing a lookup of the memory address to produce an attribute that is associated with the memory address;

marking the cache line with an aging indicator that is based on the attribute, wherein the marked aging indicator is one of a slow aging indicator and a normal aging indicator; and

in response to marking with the slow aging indicator, preventing the cache line from aging as would another cache line that is marked with the normal aging indicator.

11. The method of claim 10 wherein the produced attribute, that is associated with the memory address, is one of cacheable, un-cacheable and real time.

12. The method of claim 11 wherein the cache line is marked with the slow aging indicator when the attribute is real time, and with the normal aging indicator when the attribute is cacheable.

13. The method of claim 11 wherein when marked with the slow aging indicator, the cache line is prevented from aging at all.

14. The method of claim 11 wherein the memory address is a physical memory address.

15. The method of claim 11 wherein preventing the cache line from aging comprises:

incrementing an age counter associated with said another cache line, in accordance with the replacement policy; and

preventing an age counter associated with said cache line from being incremented in accordance with the replacement policy, while marked with the slow aging indicator.

16. A computer system comprising:

main memory having stored therein a program; and

a processor device having a cache coupled to the main memory, a cache controller coupled to the cache to manage the replacement of a plurality of cache lines in the cache, in accordance with a replacement policy, and storage that is to be configured by the program while being executed by the processor device to define a memory map having a cacheable region, an un-cacheable region, and a real time region, wherein upon a cache miss of an address that lies in the real time region, the cache controller is to respond by loading content at said address into a cache line and wherein the loaded cache line ages more slowly than a cache line that is in the cacheable region.

17. The computer system of claim 16 wherein the storage is to be configured by the program to define the real time region as including an interrupt service routine.

18. The computer system of claim 17 wherein the storage is to be configured to define the real time region as further including an interrupt handling routine.

19. An article of manufacture comprising:

a machine-readable storage medium having stored therein a program that when executed by a processor device configures a control register of the processor device to define a real time region in a memory map for the processor device, wherein the memory map can also have a cacheable region and an un-cacheable region defined in the control register, and wherein the real time region contains code and data of an interrupt service routine that is part of the program.

20. The article of manufacture of claim 19 wherein the real time region further includes code and data of an interrupt handler routine.

21. The article of manufacture of claim 19 wherein the program is a device driver.

22. The article of manufacture of claim 19 wherein the program is an operating system program