MEMORY SYSTEM

• US 20130254495A1
• Filed: 03/14/2013
• Published: 09/26/2013
• Est. Priority Date: 03/23/2012
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Jeong-Kyoum, Choi, Jung-Hwan, Hyun, Seok-Hun
• Application Number:
  US13/804,044
• Publication Number:
  US 20130254495A1
• Time in Patent Office: Days
• US Class Current: 711/150
• CPC Class Codes: G06F 13/1663 Access to shared memory

Abstract

A memory system includes a memory controller, and first through fourth memory modules. The first memory module is directly connected to the memory controller through a first memory bus and exchanges first data with the memory controller through the first memory bus. The second memory module is directly connected to the memory controller through a second memory bus and exchanges second data with the memory controller through the second memory bus. The third memory module is connected to the first memory module through a third memory bus and exchanges the first data with the memory controller through the first and third memory buses. The fourth memory module is connected to the second memory module through a fourth memory bus and exchanges the second data with the memory controller through the second and fourth memory buses.

Claims

1. A memory system, comprising:

a memory controller;

a first memory module directly connected to the memory controller through a first memory bus, and configured to exchange first data of a plurality of data with the memory controller through the first memory bus;

a second memory module directly connected to the memory controller through a second memory bus, and configured to exchange second data of the plurality of data with the memory controller through the second memory bus, the second data being different from the first data;

a third memory module connected to the first memory module through a third memory bus, and configured to exchange the first data with the memory controller through the first memory bus and the third memory bus; and

a fourth memory module connected to the second memory module through a fourth memory bus, and configured to exchange the second data with the memory controller through the second memory bus and the fourth memory bus.

2. The memory system of claim 1, further configured to select one of the first and third memory modules as a first selected memory module based on a selection signal, and to select one of the second and fourth memory modules as a second selected memory module based on the selection signal,

wherein the memory system is configured to store first write data of write data in the first selected memory module and store second write data of the write data in the second selected memory module during a write operation mode, wherein the second write data is different from the first write data, and

wherein the memory system is configured to read first read data of read data from the first selected memory module and read second read data of the read data from the second selected memory module during a read mode, wherein the second read data is different from the first read data.

3. The memory system of claim 2, configured so that a first unselected memory module and a second unselected memory module are disabled based on the selection signal, the first unselected memory module being the other one of the first and third memory modules, the second unselected memory module being the other one of the second and fourth memory modules.

4. The memory system of claim 1, wherein the first memory module includes:

a plurality of first data input/output (I/O) pins connected to the first memory bus;

a plurality of second data I/O pins connected to the third memory bus; and

a volatile memory device connected to the plurality of first data I/O pins and the plurality of second data I/O pins,

wherein the memory system is configured to select between the volatile memory device exchanging the first data with the memory controller through the first bus and the plurality of first data I/O pins, and transmitting the first data from one of the memory controller and the third memory module to another one of the memory controller and the third memory module through the first memory bus, the plurality of first data I/O pins, the volatile memory device, the plurality of second data I/O pins and the third memory bus.

5. The memory system of claim 4, wherein the first memory module further includes a plurality of data I/O buffer units, each data I/O buffer unit has a first path and a second path, a first path indicates a path between one of the first data I/O pins and a memory core included in the volatile memory device, a second path indicates a path between the one of the first data I/O pins and one of the second data I/O pins,

wherein one of the first path and the second path is selectively enabled.

6. The memory system of claim 5, wherein each data I/O buffer includes:

a first buffer unit connected to the one of the first data I/O pins;

a second buffer unit connected to the memory core;

a third buffer unit connected to the one of the second data I/O pins; and

a path selection unit configured to connect one of the second buffer unit and the third buffer unit to the first buffer unit based on a selection signal.

7. The memory system of claim 6, wherein another one of the second buffer unit and the third buffer unit that is not connected to the first buffer unit is disabled based on the selection signal.

8. The memory system of claim 1, wherein a distance between the memory controller and the second memory module is longer or shorter than a distance between the memory controller and the fourth memory module.

9. The memory system of claim 1, further comprising:

a fifth memory module connected to the third memory module through a fifth memory bus, and configured to exchange the first data with the memory controller through the first memory bus, the third memory bus and the fifth memory bus.

10. The memory system of claim 9, further comprising:

a sixth memory module connected to the fourth memory module through a sixth memory bus, and configured to exchange the second data with the memory controller through the second memory bus, the fourth memory bus and the sixth memory bus.

11. The memory system of claim 1, further comprising:

a fifth memory module directly connected to the memory controller through a fifth memory bus, and configured to exchange third data of the plurality of data with the memory controller through the fifth memory bus, the third data being different from the first data and the second data;

a sixth memory module directly connected to the memory controller through a sixth memory bus, and configured to exchange fourth data of the plurality of data with the memory controller through the sixth memory bus, the fourth data being different from the first data, the second data and the third data;

a seventh memory module connected to the fifth memory module through a seventh memory bus, and configured to exchange the third data with the memory controller through the fifth memory bus and the seventh memory bus; and

an eighth memory module connected to the sixth memory module through an eighth memory bus, and configured to exchange the fourth data with the memory controller through the sixth memory bus and the eighth memory bus.

12. The memory system of claim 1, wherein the memory controller and the first, second, third and fourth memory modules are mounted on a base substrate,

wherein the first, second, third and fourth memory buses are provided such that a plurality of data lines that are formed on the base substrate are selectively electrically opened or shorted.

13. A memory system, comprising:

a memory controller;

a first memory bus configured to connect the memory controller to a first memory module, and to transmit first write data to the first memory module;

a second memory bus configured to connect the memory controller to a second memory module, and to transmit the second write data to the second memory module, the second write data being different from the first write data, wherein the memory system is configured to simultaneously transmit the first write data and the second write data from the memory controller;

a third memory bus configured to connect the first memory module to a third memory module, and to transmit the first write data received via the first memory bus to the third memory module; and

a fourth memory bus configured to connect the second memory module to a fourth memory module, and to transmit the second write data received via the second memory bus to the fourth memory module.

14. The memory system of claim 13, further configured to transmit first read data to the memory controller through the first memory bus when the first read data is stored in the first memory module, and to transmit the first read data to the memory controller through the first memory bus and the third memory bus when the first read data is stored in the third memory module, and

further configured to transmit second read data to the memory controller through the second memory bus when the second read data is stored in the second memory module, and to transmit the second read data to the memory controller through the second memory bus and the fourth memory bus when the second read data is stored in the fourth memory module, the second read data being different from the first read data, wherein the memory system is configured so that the memory controller simultaneously receives the first read data and the second read data.

15. A memory system, comprising:

a controller;

a first memory module including at least a first memory device having a first memory core;

a first bus between the controller and the first memory module;

a second memory module including at least a second memory device having a second memory core; and

a second bus between the first memory module and the second memory module,

wherein;

the first bus is selectively electrically connected to the second bus; and

the first bus is selectively electrically connected to the first memory core.

16. The memory system of claim 15, further comprising:

a third memory module including at least a third memory device having a third memory core;

a third bus between the controller and the third memory module;

a fourth memory module including at least a fourth memory device having a fourth memory core; and

a fourth bus between the third memory module and the fourth memory module.

17. The memory system of claim 16, wherein:

the controller is connected to each of the first memory module and the third memory module in a point-to-point manner;

the first memory module is connected to the second memory module in a point-to-point manner; and

the third memory module is connected to the fourth memory module in a point-to-point manner.

18. The memory system of claim 16, wherein:

the memory system is configured so that;

the controller transmits data directly to the first memory module and transmits data directly to the third memory module; and

the controller transmits data to the second memory module through the first memory module, and transmits data to the fourth memory module through the third memory module.

19. The memory system of claim 18, wherein:

the memory system is further configured so that;

the controller transmits data directly to the first memory module and simultaneously transmits data directly to the third memory module; and

the controller transmits data indirectly to the second memory module and simultaneously transmits data indirectly to the fourth memory module.

20. The memory system of claim 19, wherein:

the memory system is further configured so that;

the controller receives data directly from the first memory module and simultaneously receives data directly from the third memory module; and

the controller receives data indirectly from the second memory module and simultaneously receives data indirectly from the fourth memory module.