SEMICONDUCTOR DEVICE
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Abstract
An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which stored data can be stored even when power is not supplied in a data storing time and there is no limitation on the number of times of writing. The semiconductor device includes a first transistor which includes a first channel formation region using a semiconductor material other than an oxide semiconductor, a second transistor which includes a second channel formation region using an oxide semiconductor material, and a capacitor. One of a second source electrode and a second drain electrode of the second transistor is electrically connected to one electrode of the capacitor.
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Citations
17 Claims
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1. (canceled)
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2. A semiconductor device comprising:
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a transistor comprising; a first oxide semiconductor layer over a substrate; a second oxide semiconductor layer over the first oxide semiconductor layer; a source electrode and a drain electrode over and in contact with the second oxide semiconductor layer; a gate insulating layer over the source electrode and the drain electrode; and a gate electrode over the gate insulating layer, wherein an edge portion of each of the source electrode and the drain electrode is tapered. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9)
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10. A semiconductor device comprising:
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a first transistor comprising; a semiconductor layer over a substrate; a first gate insulating layer over the semiconductor layer; and a first gate electrode over the first gate insulating layer, an interlayer insulating film over the first transistor; and a second transistor over the interlayer insulating film, the second transistor comprising; a first oxide semiconductor layer over the interlayer insulating film; a second oxide semiconductor layer over the first oxide semiconductor layer; a source electrode and a drain electrode over and in contact with the second oxide semiconductor layer; a gate insulating layer over the source electrode and the drain electrode; and a gate electrode over the gate insulating layer, wherein an edge portion of each of the source electrode and the drain electrode is tapered. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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Specification