THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF

• US 20130256666A1
• Filed: 03/18/2013
• Published: 10/03/2013
• Est. Priority Date: 03/28/2012
• Status: Abandoned Application

• Current Assignee: Dongguan Masstop Liquid Crystal Display Company Limited (Wintek Corporation), Wintek Corporation
• Original Assignee: Dongguan Masstop Liquid Crystal Display Company Limited (Wintek Corporation), Wintek Corporation
• Inventors: Chang, Hui-Yu, Yu, Ming-Chang, Han, Hsi-Rong, Chiou, Chang-Ching
• Application Number:
  US13/846,896
• Publication Number:
  US 20130256666A1
• Time in Patent Office: Days
• US Class Current: 257/57
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A thin film transistor and a manufacturing method thereof are provided. The thin film transistor includes a gate, an oxide channel layer, a gate insulating layer, a source, a drain and a dielectric layer. The gate is disposed on a substrate. The oxide channel layer, disposed on the substrate, is stacked with the gate. A material of the oxide channel layer includes a metal element. The metal element content shows a gradient distribution along a thickness direction of the oxide channel layer. The gate insulation layer is disposed between the gate and the oxide channel layer. The source and the drain are disposed in parallel to each other, and connected to the oxide channel layer. Sides of the source and the drain, facing away from the substrate, are covered by the dielectric layer.

Claims

1. A thin film transistor, comprising:

a gate disposed on a substrate;

an oxide channel layer disposed on the substrate and stacked with the gate in a top and bottom manner, wherein a material of the oxide channel layer comprises a metal element and the metal element content has a gradient distribution in a thickness direction of the oxide channel layer;

a gate insulation layer disposed between the gate and the oxide channel layer;

a source;

a drain configured parallel to the source and the source and the drain being connected to the oxide channel layer; and

a dielectric layer covering the source and the drain at a side away from the substrate.

2. The thin film transistor as claimed in claim 1, wherein the oxide channel layer has a first region and a second region, the metal element content in the first region is greater than the metal element content in the second region while the first region and the second region are sequentially arranged along the thickness direction and the first region is closer to the gate than the second region, and the metal element content is substantially gradually reduced from the first region to the second region.

3. The thin film transistor as claimed in claim 1, wherein the oxide channel layer has a first region and a second region, the metal element content in the first region is greater than the metal element content in the second region while the first region and the second region are sequentially arranged along the thickness direction and the first region is closer to the source and the drain than the second region, and the metal element content is substantially gradually reduced from the first region to the second region.

4. The thin film transistor as claimed in claim 1, wherein the gate is disposed between the oxide channel layer and the substrate.

5. The thin film transistor as claimed in claim 4, further comprising an etching stop layer located at a side of the oxide channel layer, wherein the side is in contact with the source and the drain.

6. The thin film transistor as claimed in claim 4, wherein the source and the drain are disposed between the oxide channel layer and the gate.

7. The thin film transistor as claimed in claim 1, wherein the oxide channel layer is located between the substrate and the gate, the thin film transistor further comprises an insulation layer located at a side of the gate away from the gate insulation layer, the insulation layer has a first through hole and a second through hole passing through the insulation layer and the gate insulation layer to partially expose the oxide channel layer, and the source and the drain are connected to the oxide channel layer through the first through hole and the second through hole.

8. The thin film transistor as claimed in claim 1, wherein the metal element comprises In, Zn, Cd, or Sn.

9. A manufacturing method of a thin film transistor (TFT), comprising:

forming a gate on a substrate;

forming at least one first semiconductor oxide layer and at least one second semiconductor oxide layer on the substrate, wherein the at least one first semiconductor oxide layer and the at least one second semiconductor oxide layer are alternately arranged to form an oxide channel layer, the oxide channel layer is disposed on the substrate and stacked with the gate in a top and bottom manner, a material of the oxide channel layer comprises a metal element, and the metal element content has a gradient distribution in a thickness direction of the oxide channel layer;

forming a gate insulation layer between the gate and the oxide channel layer;

forming a source and a drain, wherein the source and the drain are configured parallel to each other and connected to the oxide channel layer; and

forming a dielectric layer covering the source and the drain at a side away from the substrate.

10. The manufacturing method of the TFT as claimed in claim 9, wherein the step of forming the first semiconductor oxide layer comprises:

performing a low temperature film forming process, and a fabrication temperature of the low temperature film forming process ranges from 20°

C. to 150°

C.

11. The manufacturing method of the TFT as claimed in claim 9, wherein the metal element content in the at least one first semiconductor oxide layer is a first content, the metal element content in the at least one second semiconductor oxide layer is a second content different to the first content.

12. The manufacturing method of the TFT as claimed in claim 11, further comprising performing a thermal annealing process to diffuse the metal element from the at least one first semiconductor oxide layer to the at least one second semiconductor oxide layer so that the gradient distribution of the metal element content is substantially a gradual change distribution to form the oxide channel layer.