Gate Overvoltage Protection for Compound Semiconductor Transistors
First Claim
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1. A transistor device, comprising:
- a compound semiconductor body;
a drain disposed in the compound semiconductor body;
a source disposed in the compound semiconductor body and spaced apart from the drain by a channel region;
a gate operable to control the channel region; and
a gate overvoltage protection device connected between the source and the gate and comprising p-type and n-type silicon-containing semiconductor material.
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Abstract
A transistor device includes a compound semiconductor body, a drain disposed in the compound semiconductor body and a source disposed in the compound semiconductor body and spaced apart from the drain by a channel region. A gate is provided for controlling the channel region. The transistor device further includes a gate overvoltage protection device connected between the source and the gate, the gate overvoltage protection device including p-type and n-type silicon-containing semiconductor material.
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Citations
36 Claims
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1. A transistor device, comprising:
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a compound semiconductor body; a drain disposed in the compound semiconductor body; a source disposed in the compound semiconductor body and spaced apart from the drain by a channel region; a gate operable to control the channel region; and a gate overvoltage protection device connected between the source and the gate and comprising p-type and n-type silicon-containing semiconductor material. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A transistor device, comprising:
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a GaN semiconductor body; a drain disposed in the GaN semiconductor body; a source disposed in the GaN semiconductor body and spaced apart from the drain by a channel region; a gate operable to control the channel region; and a gate overvoltage protection device disposed in a first trench formed in the GaN semiconductor body and connected between the source and the gate, the gate overvoltage protection device comprising alternating p-type and n-type silicon regions. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28)
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29. A method of manufacturing a transistor device, comprising:
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forming a drain and a source in a GaN semiconductor body with the drain and the source spaced apart by a channel region; forming a gate operable to control the channel region; forming a first trench in the GaN semiconductor body; and forming a gate overvoltage protection device connected between the source and the gate, the gate overvoltage protection device comprising alternating p-type and n-type silicon regions disposed in the first trench. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36)
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Specification