TRANSISTOR, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR MODULE INCLUDING THE SAME

• US 20130256770A1
• Filed: 02/27/2013
• Published: 10/03/2013
• Est. Priority Date: 03/29/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yamada, Satoru, Lim, Jun-Hee, Huh, Ki-Jae, Jang, Sung-Ho
• Granted Patent: US 8,901,630 B2
• Time in Patent Office: Days
• US Class Current: 257/296
• CPC Class Codes: H01L 27/04 the substrate being a semiconductor body
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device including a buried cell array transistor and an electronic device including the same are provided. The device includes a field region in a substrate and the filed region defines an active region. A first source/drain region and a second source/drain region are in the active region. A gate trench is between the first and second source/drain regions, and in the active region and the field region. A gate structure is within the gate trench. The gate structure includes a gate electrode, an insulating gate capping pattern on the gate electrode, a gate dielectric between the gate electrode and the active region, and an insulating metal-containing material layer between the insulating gate capping pattern and the active region.

Claims

1. A semiconductor device comprising:

an active region in a substrate;

a field region defining the active region;

a first source/drain region and a second source/drain region in the active region;

a gate trench in the active region and the field region, the gate trench being between the first and second source/drain regions in the active region; and

a gate structure within the gate trench,

wherein the gate structure comprises;

a gate electrode;

a gate dielectric between the gate electrode and the active region;

an insulating gate capping pattern on the gate electrode; and

an insulating metal-containing material layer between the insulating gate capping pattern and the active region, the insulating metal-containing material layer being at least partially within the gate trench.

2. The device of claim 1, wherein the first source/drain region and the second source/drain region have an N conductivity type, and the insulating metal-containing material layer includes a metal having a Fermi energy closer to a conduction band of an energy band diagram of the active region than to a valance band of the energy band diagram of the active region.

3. The device of claim 2, wherein the insulating metal-containing material layer includes one of lanthanum oxide, lanthanum oxynitride, magnesium oxide and magnesium oxynitride.

4. The device of claim 1, wherein the first source/drain region and the second source/drain region have a P conductivity type, and the insulating metal-containing material layer includes a metal having a Fermi energy closer to a valance band of an energy band diagram of the active region than to a conduction band of the energy band diagram of the active region.

5. The device of claim 4, wherein the insulating metal-containing material layer includes one of aluminum oxide, aluminum oxynitride, tantalum oxide, tantalum oxynitride, iridium oxide and iridium oxynitride.

6. The device of claim 1, wherein the gate dielectric includes silicon oxide or nitrogen-doped silicon oxide, the insulating metal-containing material layer includes a metal different from the gate dielectric, and the metal includes one of lanthanum, magnesium, aluminum, tantalum and iridium.

7. The device of claim 1, wherein the gate dielectric includes a first gate dielectric portion between the active region and the gate electrode and a second gate dielectric portion between the active region and the insulating gate capping pattern.

8. The device of claim 7, wherein the insulating metal-containing material layer is in the second gate dielectric portion.

9. The device of claim 8, wherein the insulating metal-containing material layer includes a portion extending toward the first gate dielectric portion and overlapping with a portion of the gate electrode.

10. The device of claim 7, wherein the insulating metal-containing material layer includes a first portion between the insulating gate capping pattern and the second gate dielectric portion, and a second portion between the insulating gate capping pattern and the gate electrode.

11. The device of claim 1, wherein an edge portion of a surface of the gate electrode protrudes toward the insulating gate capping pattern, and the insulating metal-containing material layer covers the surface of the gate electrode including the edge portion.

12. The device of claim 1, wherein a portion of either one of the first source/drain region and the second source/drain region overlapping with the insulating metal-containing material layer is larger than a portion of one of the first source/drain region and the second source/drain region overlapping with the gate electrode.

13. The device of claim 1, wherein a portion of either one of the first source/drain region and the second source/drain region overlapping with the insulating gate capping pattern is larger than a portion of one of the first source/drain region and the second source/drain region overlapping with the gate electrode.

14. The device of claim 1, wherein the second source/drain region has a shallower junction structure than the first source/drain region.

15. The device of claim 14, further comprising:

a bit line structure electrically connected to the first source/drain region; and

a capacitor structure electrically connected to the second source/drain region.

16. The device of claim 1, wherein the gate trench has smaller width in the active region than in the field region.

17. A semiconductor device comprising:

an active region in a substrate;

a first source/drain region and a second source/drain region in the active region;

a gate trench in the active region between the first source/drain region and the second source/drain region; and

a gate structure within the gate trench,

wherein the gate structure comprises;

a gate electrode at least partially overlapping with the first and second source/drain regions;

an insulating metal-containing material layer on the gate electrode and within the gate trench, the insulating metal-containing material layer at least partially overlapping with the first and second source/drain regions; and

a gate dielectric between the gate electrode and the active region,

wherein the gate electrode includes a conductive material having a Fermi energy closer to a mid-gap energy of the active region than to a valance band or conduction band of an energy band diagram of the active region and having a first work function, and the insulating metal-containing material layer includes a metal having a second work function less than the first work function.

18. The device of claim 17, wherein the insulating metal-containing material layer includes a dielectric material containing a material different from the gate dielectric.

19. The device of claim 17, wherein the insulating metal-containing material layer includes a dipole layer.

20. The device of claim 17, wherein a portion of either one of the first and second source/drain regions overlapping with the insulating metal-containing material layer is larger than a portion of the one of the first and second source/drain regions overlapping with the gate electrode.

21. A semiconductor device comprising:

a field region in a substrate, the field region defining a cell active region and a peripheral active region;

a first cell source/drain region and a second cell source/drain region in the cell active region;

a cell gate trench in the cell active region between the first cell source/drain region and the second cell source/drain region;

a cell gate structure within the cell gate trench;

a first peripheral source/drain region and a second peripheral source/drain region in the peripheral active region; and

a peripheral gate structure on the peripheral active region,

wherein the peripheral gate structure includes a peripheral gate dielectric and a peripheral gate electrode, and

wherein the cell gate structure comprises;

a cell gate electrode and an insulating cell gate capping pattern stacked sequentially;

a cell gate dielectric between the cell gate electrode and the cell active region;

an insulating metal-containing material layer on the cell gate electrode and within the cell gate trench, the insulating metal-containing material layer overlapping at least partially with the first and second source/drain regions and including a metal different from the cell gate dielectric.

22. The device of claim 21, wherein the cell gate electrode includes a conductive material having a Fermi energy closer to a mid-gap energy of the cell active region than to a valance band or conduction band of an energy band diagram of the cell active region, and the metal in the insulating metal-containing material layer has a Fermi energy closer to the valance band or conduction band of the cell active region than to the mid-gap energy of the cell active region.

23-47. -47. (canceled)

48. A semiconductor device comprising:

an active region in a substrate;

a first source/drain region, a second source/drain region and a channel region therebetween in the active region;

a gate trench between the first and second source/drain regions, the gate trench having sides defining a trench opening; and

a gate structure within the gate trench,

wherein the gate structure comprises;

a gate electrode having a first gate electrode portion overlapping with the first and second source/drain regions and a second gate electrode portion overlapping with the channel region;

a gate dielectric between the gate electrode and the active region;

an insulating gate capping pattern on the gate electrode, the insulating gate capping pattern being between the trench opening and the gate electrode; and

a supplemental gate electrode pattern at least partially overlapping with the first and second source/drain regions, and being configured to provide a difference between work functions of the first gate electrode portion and the first and second source/drain regions that is less than a difference between work functions of the second gate electrode portion and the first and second source/drain regions.

49. The device of claim 48, the second gate electrode portion has a Fermi energy closer to a mid-gap energy of an energy band diagram of the active region than to a conduction band or valance band of the active region.

50. The device of claim 48, wherein the supplemental gate electrode pattern comprises an insulating metal-containing material layer.

51. The device of claim 50, wherein the first source/drain region and the second source/drain region comprise an N conductivity type, and the insulating metal-containing material layer comprises a metal having a Fermi energy closer to a conduction band of an energy band diagram of the active region than to a valance band of the energy band diagram of the active region.

52. The device of claim 51, wherein the insulating metal-containing material layer comprises one of lanthanum oxide, lanthanum oxynitride, magnesium oxide and magnesium oxynitride.

56. The device of claim 50, wherein the insulating metal-containing material layer includes a dipole layer.

58. The device of claim 50, wherein the first gate electrode portion includes a conductive pattern overlapping with the first and second source/drain regions and, the conductive pattern having a work function different from that of the second gate electrode portion.

59. The device of claim 58, wherein the first and second source/drain regions comprise an N conductivity type, and the conductive pattern has a Fermi energy closer to a conduction band of an energy band diagram of the active region than to a mid-gap energy of the energy band diagram of the active region.

53-55. -55. (canceled)

57. (canceled)

60-78. -78. (canceled)