METAL GATE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THEREOF

• US 20130256805A1
• Filed: 03/30/2012
• Published: 10/03/2013
• Est. Priority Date: 03/30/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Hui-Wen, Young, Bao-Ru, Chuang, Hak-Lay, Zhu, Ming
• Granted Patent: US 8,772,114 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A method of semiconductor fabrication including forming a first work function metal layer on a first region of the substrate and forming a metal layer on the first work function metal layer and on a second region of the substrate. A dummy layer is formed on the metal layer. The layers are then patterned to form a first gate structure in the first region and a second gate structure in the second region of the substrate. The dummy layer is then removed to expose the metal layer, which is treated. The treatment may be an oxygen treatment that allows the metal layer to function as a second work function layer.

Claims

1. A method, comprising:

forming a first work function metal layer on a first region of the substrate;

forming a metal layer on the first work function metal layer in the first region and on a second region of the substrate;

forming a dummy layer on the metal layer;

patterning the dummy layer, first work function metal layer, and the metal layer to form a first gate structure in the first region and a second gate structure in the second region of the substrate, wherein the first gate structure includes the dummy layer, the first work function metal layer and the metal layer and the second gate structure includes the dummy layer and the metal layer;

after forming the first gate structure and the second gate structure, removing the dummy layer to expose the metal layer; and

treating the metal layer.

2. The method of claim 1, wherein the treating includes an oxygen treatment.

3. The method of claim 1, wherein the treating includes transforming a composition of the metal layer.

4. The method of claim 3, wherein the transformed composition provides a work function for a p-type device.

5. The method of claim 3, wherein the transforming the composition includes transforming from a TiN composition to a TiON composition.

6. The method of claim 1, wherein the first gate structure is associated with an nFET device, and the second gate structure is associated with a pFET device.

7. The method of claim 1, wherein the first work function metal layer includes a capping layer and another metal layer.

8. The method of claim 7, wherein the fill layer includes a blocking layer and a filler metal layer.

9. A method, comprising:

forming a portion of a first gate structure associated with a NMOS transistor, wherein the portion of the first gate structure includes a gate dielectric, a capping layer, a first metal layer on the capping layer, and a second metal layer overlying the first metal layer, wherein the first metal layer is an n-type metal;

forming a portion of a second gate structure associated with a PMOS transistor, wherein the portion of the second gate structure includes the gate dielectric and the second metal layer formed on the gate dielectric, and wherein the second gate structure does not include the first metal layer;

forming a dummy layer on the portion of the first gate structure and on the portion of the second gate structure overlying the second metal layer;

removing the dummy layer simultaneously in both the first gate structure and the second gate structure to form trenches; and

filling the trenches with a fill metal.

10. The method of claim 9, further comprising:

treating the second metal layer after removing the dummy layer and before filling the trenches.

11. The method of claim 10, wherein the treating introduces oxygen to the second metal layer.

12. The method of claim 9, wherein the forming the portion of the second gate structure includes forming the second metal layer directly on the gate dielectric.

13. The method of claim 9, wherein the forming the portion of the first gate structure includes:

forming the gate dielectric layer on a substrate in a first and second region of the substrate;

forming a capping layer and the first metal layer on the substrate and patterning the capping layer and the first metal layer to be disposed only on the first region of the substrate;

forming the second metal layer on the substrate on the first and second regions of the substrate; and

patterning the gate dielectric layer, the capping layer, the first metal layer, and the second metal layer to form the portion of the first gate structure in the first region of the substrate.

14. The method of claim 9, wherein the dummy layer is polysilicon.

15. A device, comprising:

a first gate structure including;

a first type of work function material;

a second type of work function material overlying the first type of work function material, wherein the second type of work function material includes oxygen; and

a fill layer overlying the second type of work function material; and

a second gate structure including;

the second type of work function material; and

the fill layer overlying the second type of work function material.

16. The device of claim 15, wherein the first gate structure is associated with an NMOS device, and wherein the second gate structure is associated with a PMOS device.

17. The device of claim 15, wherein the fill layer includes a blocking layer and a filler metal layer.

18. The device of claim 15, wherein each of the first and second gate structures include a gate dielectric layer underlying the first or second type of work function material, and wherein the gate dielectric layer includes a high-k dielectric material.

19. The device of claim 15, wherein the second type of work function material is TiON.

20. The device of claim 15, wherein the first type of work function material includes a bi-layer including a capping layer and a metal layer.