PACKAGING SUBSTRATE, SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF

• US 20130256915A1
• Filed: 09/13/2012
• Published: 10/03/2013
• Est. Priority Date: 04/02/2012
• Status: Abandoned Application

• Current Assignee: Siliconware Precision Industries Co., Ltd.
• Original Assignee: Siliconware Precision Industries Co., Ltd.
• Inventors: Chiu, Chi-Hsin, Huang, Huei-Nuan, Lin, Chun-Tang, Chan, Chien-Feng
• Application Number:
  US13/614,590
• Publication Number:
  US 20130256915A1
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/26175 Flow barriers
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81192 wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06582 Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA

Abstract

A semiconductor package includes a packaging substrate having a die attach area, a plurality of flow-guiding blocks disposed around an outer periphery of the die attach area, a first semiconductor element mounted on the die attach area, a second semiconductor element mounted on the first semiconductor element, and an underfill formed between the packaging substrate and the second semiconductor element. During filling of the underfill between the packaging substrate and the second semiconductor element, the flow-guiding blocks can guide a portion of the underfill to flow between the first semiconductor element and the second semiconductor element such that only one dispensing process is required for the underfill to completely encapsulate all conductive bumps used for flip-chip interconnection, thereby simplifying the fabrication process and improving the production efficiency.

Claims

1. A semiconductor package, comprising:

a packaging substrate having a die attach area;

a plurality of first flow-guiding blocks disposed around an outer periphery of the die attach area of the packaging substrate;

a first semiconductor element mounted on the die attach area;

a second semiconductor element mounted on the first semiconductor element; and

an underfill formed between the packaging substrate and the second semiconductor element for encapsulating the first semiconductor element and the first flow-guiding blocks.

2. The semiconductor package of claim 1, wherein a height of each of the first flow-guiding blocks is greater than or equal to that of the first semiconductor element.

3. The semiconductor package of claim 1, wherein the first semiconductor element is mounted on the die attach area in a flip-chip manner.

4. The semiconductor package of claim 1, wherein a gap is formed between a surface of the first semiconductor element and a top of each of the first flow-guiding blocks.

5. The semiconductor package of claim 1, wherein the second semiconductor element is of a surface area greater than that of the first semiconductor element

6. The semiconductor package of claim 1, wherein a gap is formed between a surface of the second semiconductor element and a top of each of the first flow-guiding blocks.

7. The semiconductor package of claim 1, further comprising a third semiconductor element and a fourth semiconductor element disposed between the first semiconductor element and the second semiconductor element.

8. The semiconductor package of claim 7, wherein the first semiconductor element has a bonding area and a plurality of second flow-guiding blocks disposed around an outer periphery of the bonding area, the third semiconductor element is bonded to the bonding area, and the fourth semiconductor element is interposed between the second semiconductor element and the third semiconductor element.

9. The semiconductor package of claim 7, wherein the area of fourth semiconductor element is greater in area than the third semiconductor element.

10. The semiconductor package of claim 7, wherein the underfill further encapsulates the second flow-guiding blocks, the third semiconductor element and the fourth semiconductor element.

11. A fabrication method of a semiconductor package, comprising the steps of:

providing a packaging substrate having a die attach area and a plurality of first flow-guiding blocks disposed around an outer periphery of the die attach area;

mounting a first semiconductor element on the die attach area;

mounting a second semiconductor element on the first semiconductor element; and

forming an underfill between the packaging substrate and the second semiconductor element for encapsulating the first semiconductor element and the first flow-guiding blocks.

12. The fabrication method of claim 11, wherein a height of each of the first flow-guiding blocks is greater than or equal to that of the first semiconductor element.

13. The fabrication method of claim 11, wherein the first semiconductor element is mounted on the die attach area in a flip-chip manner.

14. The fabrication method of claim 11, wherein a gap is formed between a surface of the first semiconductor element and a top of each of the first flow-guiding blocks.

15. The fabrication method of claim 11, wherein the second semiconductor element is greater in area than the first semiconductor element.

16. The fabrication method of claim 11, wherein a gap is formed between a surface of the second semiconductor element and a top of each of the first flow-guiding blocks.

17. The fabrication method of claim 11, further comprising disposing a third semiconductor element and a fourth semiconductor element between the first semiconductor element and the second semiconductor element.

18. The fabrication method of claim 17, wherein the first semiconductor element has a bonding area and a plurality of second flow-guiding blocks formed around an outer periphery of the bonding area, the third semiconductor element is bonded to the bonding area, and the fourth semiconductor element is interposed between the second semiconductor element and the third semiconductor element.

19. The fabrication method of claim 17, wherein the fourth semiconductor element is greater in area than the third semiconductor element

20. The fabrication method of claim 17, wherein the underfill encapsulates the second flow-guiding blocks, the third semiconductor element and the fourth semiconductor element.

21. A packaging substrate, comprising:

a substrate body having a die attach area; and

a plurality of first flow-guiding blocks disposed around an outer periphery of the die attach area.