SEMICONDUCTOR TESTING APPARATUS

• US 20130257470A1
• Filed: 12/12/2011
• Published: 10/03/2013
• Est. Priority Date: 12/16/2010
• Status: Abandoned Application

• Current Assignee: Semicontest Co., Ltd.
• Original Assignee: Semicontest Co., Ltd.
• Inventors: Park, Sung-Hak
• Application Number:
  US13/994,074
• Publication Number:
  US 20130257470A1
• Time in Patent Office: Days
• US Class Current: 324/756.02
• CPC Class Codes: G01R 1/045 Sockets or component fixtures for RF or HF testing
• CPC Class Codes: G01R 1/0483 Sockets for un-leaded IC's having matrix type contact fields, e.g. BGA or PGA devices; Sockets for unpackaged, naked chips for IC's with connecting points around the edges only G01R1/0433
• CPC Class Codes: G01R 31/2601 Apparatus or methods therefor G01R31/2607, G01R31/2642 take precedence
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2924/15174 in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H05K 1/0231 Capacitors or dielectric substances
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 2201/10636 Leadless chip, e.g. chip capacitor or resistor
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A semiconductor testing apparatus is provided wherein components that must be arranged most closely are arranged most closely to terminals of a test object. The present apparatus is semiconductor testing apparatus comprising a printed circuit board, and a test socket mounted on an upper surface of the printed circuit board and forming a signal connection path between a test object and the printing circuit board, wherein a chip shaped capacitor is mounted on the upper surface of the printed circuit board, an interference avoidance space avoiding contact with the capacitor is formed in the test socket, the interference avoidance space being formed at a location facing the location where the capacitor is mounted, and the capacitor and the test socket being non-contacted from each other by the interference avoidance space.

Claims

1. A semiconductor testing apparatus comprising a printed circuit board, and a test socket mounted on an upper surface of the printed circuit board and forming a signal connection path between a test object and the printing circuit board,

wherein a chip shaped capacitor is mounted on the upper surface of the printed circuit board, an interference avoidance space avoiding contact with the capacitor is formed in the test socket, the interference avoidance space being formed at a location facing the location where the capacitor is mounted, and

the capacitor and the test socket being non-contacted from each other by the interference avoidance space.

2. The semiconductor testing apparatus according to claim 1,

wherein the interference avoidance space is formed in a groove shape on a bottom surface of the test socket.

3. The semiconductor testing apparatus according to claim 1,

wherein the interference avoidance space is a hole punched perpendicularly to the test socket.

4. The semiconductor testing apparatus according to claim 1,

wherein a via hole for interlayer movement of a signal line is formed on the printed circuit board, the via hole penetrating the upper surface and a bottom surface of the printed circuit board where the capacitor is mounted.

5. A semiconductor testing apparatus comprising a printed circuit board, and a test socket mounted on an upper surface of the printed circuit board and forming a signal connection path between a test object and the printing circuit board,

wherein the test socket comprises a lower socket mounted on the upper surface of the printed circuit board;

a middle circuit board mounted on an upper surface of the lower socket; and

an upper socket mounted on an upper surface of the middle circuit board;

the middle circuit board is bigger than the upper socket and a spare mounting space big enough to have space left even after the upper socket is mounted thereon is formed on the upper middle circuit board, and a component for signal improvement is mounted on the spare mounting space.

6. The semiconductor testing apparatus according to claim 5,

wherein the lower socket is smaller than the printed circuit board and bigger than the upper socket.

7. The semiconductor testing apparatus according to claim 5,

wherein the lower socket and the upper socket each comprises a same number of conductive material tracks, and the middle circuit board comprises a same number of signal tracks as the number of conductive material tracks, and

each of the conductive material tracks of the lower socket and the upper socket and the signal tracks is connected one by one, and connected to a corresponding signal track of the printed circuit board.