SEMICONDUCTOR DEVICE
First Claim
1. A semiconductor device comprising:
- a memory cell comprising;
a first transistor;
a second transistor over the first transistor; and
a third transistor over the second transistor,wherein one of a source and a drain of the second transistor is electrically connected to a gate of the first transistor, andwherein one of a source and a drain of the third transistor is electrically connected to the gate of the first transistor.
1 Assignment
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Accused Products
Abstract
A nonvolatile semiconductor device is provided. Each memory cell in a semiconductor device includes a D/A converter and an amplifier transistor. An output voltage of the D/A converter is stored as data in the memory cell, whereby two or more bits of data can be stored in the memory cell. By stacking transistors of the D/A converter with an interlayer film provided therebetween and using the parasitic resistance of a conductive material provided in a contact hole formed in the interlayer film as a resistor of the D/A converter, the area of the memory cell can be reduced. The transistor includes an oxide semiconductor in a channel formation region. Accordingly, a nonvolatile semiconductor device can be easily obtained.
45 Citations
20 Claims
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1. A semiconductor device comprising:
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a memory cell comprising; a first transistor; a second transistor over the first transistor; and a third transistor over the second transistor, wherein one of a source and a drain of the second transistor is electrically connected to a gate of the first transistor, and wherein one of a source and a drain of the third transistor is electrically connected to the gate of the first transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor device comprising:
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a first memory cell; a second memory cell; a third memory cell; a first write selection line electrically connected to the first memory cell and the second memory cell; a second write selection line electrically connected to the third memory cell; a first write data line electrically connected to the first memory cell and the third memory cell; a second write data line electrically connected to the first memory cell and the third memory cell; a third write data line electrically connected to the second memory cell; a fourth write data line electrically connected to the second memory cell; a first read data line electrically connected to the first memory cell and the third memory cell; and a second read data line electrically connected to the second memory cell, wherein each of the first memory cell, the second memory cell, and the third memory cell comprises a first transistor, a second transistor, and a third transistor, wherein one of a source and a drain of the second transistor of each of the first memory cell, the second memory cell, and the third memory cell is electrically connected to a gate of the first transistor of each of the first memory cell, the second memory cell, and the third memory cell, and wherein one of a source and a drain of the third transistor of each of the first memory cell, the second memory cell, and the third memory cell is electrically connected to the gate of the first transistor of each of the first memory cell, the second memory cell, and the third memory cell. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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16. A semiconductor device comprising:
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a memory cell comprising; a first transistor; a second transistor over the first transistor; and a third transistor over the second transistor, wherein the first transistor and the second transistor are stacked with a first insulating layer therebetween, wherein the second transistor and the third transistor are stacked with a second insulating layer therebetween, wherein one of a source and a drain of the second transistor is electrically connected to a gate of the first transistor through a first conductor in a first contact hole in the first insulating layer, and wherein one of a source and a drain of the third transistor is electrically connected to the gate of the first transistor through a second conductor in a second contact hole in the first insulating layer, a third conductor in a third contact hole in the first insulating layer, and a fourth conductor in a fourth contact hole in the second insulating layer. - View Dependent Claims (17, 18, 19, 20)
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Specification