HANDLING OF WRITE OPERATIONS WITHIN A MEMORY DEVICE
First Claim
1. A memory device comprising:
- an array of memory cells arranged into a plurality of rows and columns and having a plurality of word lines and a plurality of bit lines passing through the array, the memory cells in each row being activated via a word line signal on the corresponding word line, and the memory cells in each column being coupled to an associated at least one bit line via which data is written into an activated memory cell of the column during a write operation and data is read from an activated memory cell of the column during a read operation;
control circuitry configured to control signals supplied to the word lines and bit lines of the array in order to control said write operation and said read operation;
a dummy column of dummy memory cells associated with said array, said dummy column including at least one dummy bit line to which said dummy memory cells are connected, the dummy memory cells including a plurality of loading dummy memory cells for providing a load to said at least one dummy bit line, and at least one write timing dummy memory cell coupled to a dummy word line;
dummy write driver circuitry coupled to said at least one dummy bit line;
the control circuitry being configured, during said write operation, to activate each of said at least one write timing dummy memory cell via the dummy word line, and to cause the dummy write driver circuitry to control a voltage on the at least one dummy bit line so as to cause a state flip condition to occur within said at least one write timing dummy memory cell; and
write detection circuitry configured, on occurrence of the state flip condition, to issue a write terminate signal to the control circuitry to terminate the write operation.
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Accused Products
Abstract
A memory device includes an array of memory cells arranged into a plurality of rows and columns and having a plurality of word lines and a plurality of bit lines passing through the array. The memory cells in each row are activated via a word line signal on the corresponding word line, and the memory cells in each column are coupled to an associated bit line pair via which data is written into an activated memory cell of the column during a write operation and data is read from the activated memory cell of the column during a read operation. A dummy column of dummy memory cells is provided and includes a plurality of loading dummy memory cells for providing a load to the at least one dummy bit line, and at least one write timing dummy memory cell coupled to a dummy word line.
18 Citations
17 Claims
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1. A memory device comprising:
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an array of memory cells arranged into a plurality of rows and columns and having a plurality of word lines and a plurality of bit lines passing through the array, the memory cells in each row being activated via a word line signal on the corresponding word line, and the memory cells in each column being coupled to an associated at least one bit line via which data is written into an activated memory cell of the column during a write operation and data is read from an activated memory cell of the column during a read operation; control circuitry configured to control signals supplied to the word lines and bit lines of the array in order to control said write operation and said read operation; a dummy column of dummy memory cells associated with said array, said dummy column including at least one dummy bit line to which said dummy memory cells are connected, the dummy memory cells including a plurality of loading dummy memory cells for providing a load to said at least one dummy bit line, and at least one write timing dummy memory cell coupled to a dummy word line; dummy write driver circuitry coupled to said at least one dummy bit line; the control circuitry being configured, during said write operation, to activate each of said at least one write timing dummy memory cell via the dummy word line, and to cause the dummy write driver circuitry to control a voltage on the at least one dummy bit line so as to cause a state flip condition to occur within said at least one write timing dummy memory cell; and write detection circuitry configured, on occurrence of the state flip condition, to issue a write terminate signal to the control circuitry to terminate the write operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method of controlling timing of a write operation within a memory device comprising an array of memory cells arranged into a plurality of rows and columns and having a plurality of word lines and a plurality of bit lines passing through the array, the memory cells in each row being activated via a word line signal on the corresponding word line, and the memory cells in each column being coupled to an associated at least one bit line via which data is written into an activated memory cell of the column during a write operation and data is read from an activated memory cell of the column during a read operation, the memory device further having control circuitry for controlling signals supplied to the word lines and bit lines of the array in order to control said write operation and said read operation, and the method comprising:
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providing a dummy column of dummy memory cells associated with said array, said dummy column including at least one dummy bit line to which said dummy memory cells are connected, the dummy memory cells including a plurality of loading dummy memory cells for providing a load to said at least one dummy bit line, and at least one write timing dummy memory cell coupled to a dummy word line; during said write operation, activating each of said at least one write timing dummy memory cell via the dummy word line, and controlling a voltage on the at least one dummy bit line so as to cause a state flip condition to occur within said at least one write timing dummy memory cell; and on occurrence of the state flip condition, issuing a write terminate signal to the control circuitry to terminate the write operation.
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17. A memory device comprising:
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an array of memory cell means arranged into a plurality of rows and columns and having a plurality of word line means and a plurality of bit line means passing through the array, the memory cell means in each row for activation via a word line signal on the corresponding word line means, and the memory cell means in each column for coupling to an associated at least one bit line means via which data is written into an activated memory cell means of the column during a write operation and data is read from an activated memory cell means of the column during a read operation; control means for controlling signals supplied to the word line means and bit line means of the array in order to control said write operation and said read operation; a dummy column of dummy memory cell means associated with said array, said dummy column including at least one dummy bit line means for connecting to said dummy memory cell means, the dummy memory cell means including a plurality of loading dummy memory cell means for providing a load to said at least one dummy bit line means; and
at least one write timing dummy memory cell means for coupling to a dummy word line means;dummy write driver means for coupling to said at least one dummy bit line means; the control means, during said write operation, for activating each of said at least one write timing dummy memory cell means via the dummy word line means; the dummy write driver means, during said write operation, for controlling a voltage on the at least one dummy bit line means so as to cause a state flip condition to occur within said at least one write timing dummy memory cell means; and write detection means, on occurrence of the state flip condition, for issuing a write terminate signal to the control means to terminate the write operation.
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Specification