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Non-Volatile Memory and Method Having a Memory Array with a High-Speed, Short Bit-Line Portion

  • US 20130258772A1
  • Filed: 03/27/2012
  • Published: 10/03/2013
  • Est. Priority Date: 03/27/2012
  • Status: Active Grant
First Claim
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1. A non-volatile memory device, comprising:

  • an array of memory cells;

    rows of word lines and columns of bit lines for accessing said array of memory cells;

    said array of memory cells being partitioned along a column direction into a first array portion and a second array portion;

    said first array portion having memory cells configured as single-level cells each storing one bit of data;

    said second portion having memory cells configured as multi-level cells each storing more than one bit of data;

    said columns of bit lines being partitioned into a first segment of bit lines corresponding to said first array portion and, a second segment of bit lines corresponding to said second array portion;

    said first segment of bit lines having first and second ends;

    said first ends being coupled adjacent to a set of read/write circuits for reading and writing in parallel a group of memory cells of said first array portion; and

    said second segment of bit lines being switchably connected to said second ends to access said set of read/write circuits via said first segment of bit lines.

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