Non-Volatile Memory and Method Having a Memory Array with a High-Speed, Short Bit-Line Portion
First Claim
1. A non-volatile memory device, comprising:
- an array of memory cells;
rows of word lines and columns of bit lines for accessing said array of memory cells;
said array of memory cells being partitioned along a column direction into a first array portion and a second array portion;
said first array portion having memory cells configured as single-level cells each storing one bit of data;
said second portion having memory cells configured as multi-level cells each storing more than one bit of data;
said columns of bit lines being partitioned into a first segment of bit lines corresponding to said first array portion and, a second segment of bit lines corresponding to said second array portion;
said first segment of bit lines having first and second ends;
said first ends being coupled adjacent to a set of read/write circuits for reading and writing in parallel a group of memory cells of said first array portion; and
said second segment of bit lines being switchably connected to said second ends to access said set of read/write circuits via said first segment of bit lines.
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Accused Products
Abstract
A non-volatile memory array is partitioned along the column direction into first and second portions. The first portion has SLC memory cells and the second portion has MLC memory cells. The first portion acts as a fast cache memory for the second portion. The read/write operations of the first portion are further enhanced by coupling to a set of read/write circuits immediately adjacent to the first portion, while the column of each bit line is switchably cut off at the junction between the first and second portions. In this way, the RC constant of the cut off bit line is at a minimum, which translates to faster precharge of the bit line via the read/write circuits. When the second portion is operating, its access to the set of read/write circuits is accomplished by not cutting off each bit line at the junction between the first and second portions.
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Citations
16 Claims
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1. A non-volatile memory device, comprising:
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an array of memory cells; rows of word lines and columns of bit lines for accessing said array of memory cells; said array of memory cells being partitioned along a column direction into a first array portion and a second array portion; said first array portion having memory cells configured as single-level cells each storing one bit of data; said second portion having memory cells configured as multi-level cells each storing more than one bit of data; said columns of bit lines being partitioned into a first segment of bit lines corresponding to said first array portion and, a second segment of bit lines corresponding to said second array portion; said first segment of bit lines having first and second ends; said first ends being coupled adjacent to a set of read/write circuits for reading and writing in parallel a group of memory cells of said first array portion; and said second segment of bit lines being switchably connected to said second ends to access said set of read/write circuits via said first segment of bit lines. - View Dependent Claims (2, 3, 4, 6, 7, 8)
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5. A non-volatile memory device as in claim wherein:
said first segment of bit lines and said second segment of bit lines respectively have RC constants in a ratio of less than or equal to 1;
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9. A method of operating a non-volatile memory device having an array of memory cells, comprising:
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accessing said array of memory cells with rows of word lines and columns of bit lines; partitioning said array of memory cells along a column direction into a first array portion and a second array portion, said first array portion being adjacent a set of read/write circuit; configuring memory cells of said first array portion to operate as single-level cells each storing one bit of data; configuring memory cells of said second portion to operate as multi-level cells each storing more than one bit of data; partitioning said columns of bit lines into a first segment of bit lines corresponding to said first array portion and a second segment of bit lines corresponding to said second array portion said first segment of bit lines having first ends adjacent the set of read/write circuits and second ends adjacent the second segment of bit lines; providing a switchable couplings between the second ends of the first segment of bit lines and the second segment of bit lines; coupling first ends of said first segment of bit lines to the set of read/write circuits and switching off the switchable coupling between the second ends of the first segment of bit lines and the second segment of bit lines when reading and writing in parallel a group of memory cells of the first array portion; and coupling first ends of said first segment of bit lines to the set of read/write circuits and switching on the switchable coupling between the second ends of the first segment of bit lines and the second segment of bit lines when reading and writing in parallel a group of memory cells of the second array portion. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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Specification