Memory System with Command Queue Reordering

• US 20130262745A1
• Filed: 03/30/2012
• Published: 10/03/2013
• Est. Priority Date: 03/30/2012
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Lin, Gary, Davidson, Matthew
• Granted Patent: US 9,135,192 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 13/1626 by reordering requests
• CPC Class Codes: G06F 13/1642 with request queuing
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A non-volatile memory system includes a memory controller that receives commands from a host and identifies commands that can be executed in parallel. The order in which commands are received is recorded so that responses may be provided to the host in the same order in which the commands were received.

Claims

1. A method of operating a nonvolatile memory system that is in communication with a host comprising:

receiving, in the memory system, a plurality of host commands from the host in a first order;

recording the first order;

subsequently identifying a second order for execution of the plurality of host commands, the second order being different from the first order;

subsequently executing the plurality of host commands in the second order; and

subsequently providing a plurality of responses to the host, corresponding to the plurality of host commands, the plurality of responses provided to the host in an order corresponding to the recorded first order.

2. The method of claim 1 wherein each of the plurality of host commands is a read command and the second order for execution provides faster reading than the first order.

3. The method of claim 2 wherein each of the plurality of responses is a return of data that was requested in a corresponding read command.

4. The method of claim 2 further comprising caching data that is read in response to a first command of the plurality of host commands while reading data in response to a second command of the plurality of host commands that was received before the first command.

5. The method of claim 1 wherein each of the plurality of host commands is a write command and the second order for execution provides faster writing than the first order.

6. The method of claim 5 wherein each of the plurality of responses is a return of an indicator that data specified in a corresponding write command was written.

7. The method of claim 1 wherein the second order for execution of the plurality of host commands interleaves host commands between a first memory die and a second memory die.

8. The method of claim 7 wherein the first memory die and the second memory die are NAND flash memory dies.

9. The method of claim 1 wherein the second order for execution of the plurality of host commands interleaves execution of host commands between a first plane and a second plane in a nonvolatile memory array.

10. The method of claim 9 wherein the nonvolatile memory array is a NAND flash memory array.

11. A nonvolatile memory system comprising:

a host interface for communication with a host;

a flash memory; and

a memory controller integrated between the host interface and the flash memory comprising;

a) a command recording module that records the order of commands received from the host;

b) a command reordering module that modifies the order of the commands received from the host prior to accessing the flash memory according to the commands; and

c) a response ordering module that sends responses to the host, each response corresponding to one of the commands, the responses sent to the host in the order of the commands received from the host as recorded in the command recording module.

12. The nonvolatile memory system of claim 11 wherein the flash memory comprises a first memory plane and a second memory plane, and wherein the command reordering module modifies the order of the commands so that the commands are interleaved between the first memory plane and the second memory plane.

13. The nonvolatile memory system of claim 11 wherein the flash memory comprises a first memory die and a second memory die, and wherein the command reordering module modifies the order of the commands so that the commands are interleaved between the first memory die and the second memory die.

14. The nonvolatile memory system of claim 11 further comprising a cache memory between the flash memory and the memory controller.

15. The nonvolatile memory system of claim 11 wherein the flash memory consists of NAND flash memory.

16. A method of reading data from a flash memory in a flash memory system comprising:

receiving a plurality of read commands from a host in a first order, the plurality of read commands including at least a first read command and a second read command, the first read command being received from the host prior to the second read command being received from the host;

recording the first order including the first read command being prior to the second read command;

reordering the plurality of read commands into a second order so that the second read command is prior to the first read command;

sending the plurality of read commands to the flash memory in the second order;

receiving data read from the flash memory according to the second order;

reordering the data read from the flash memory according to the first order; and

sending the data read from the flash memory, reordered according to the first order, to an output of the flash memory system.

17. The method of claim 16 wherein, according to the second order, the plurality of read commands are interleaved between two or more memory dies.

18. The method of claim 16 wherein, according to the second order, the plurality of read commands are interleaved between two or more planes of a flash memory array.

19. The method of claim 16 further comprising caching the data read from the flash memory prior to sending the data from the flash memory to the output of the flash memory system.