MULTIPROCESSOR SYSTEM, APPARATUS AND METHODS
First Claim
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1. A method in a multiprocessor system, the system comprising a plurality of processing elements, memory to which each of the processing elements has access, and a sequencer adapted to generate a sequence of code to be executed by the plurality of processing elements, the method comprising:
- receiving a plurality of signals during execution of the sequence of code, the signals indicating a plurality of memory access rules to be applied at instances during further execution of the sequence of code;
at said instances, applying said memory access rules for memory accesses by the plurality of processing elements; and
in the event of a memory access by a processing element violating one or more of said rules, generating a warning, signal.
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Abstract
Embodiments of the present invention provide methods and apparatus in a multiprocessor system, whereby a set of rules relating to memory access are created and implemented in a hardware element. The rules can be updated dynamically, for example by the sequence processor (or sequencer) used to control the multiple processing elements.
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Citations
14 Claims
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1. A method in a multiprocessor system, the system comprising a plurality of processing elements, memory to which each of the processing elements has access, and a sequencer adapted to generate a sequence of code to be executed by the plurality of processing elements, the method comprising:
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receiving a plurality of signals during execution of the sequence of code, the signals indicating a plurality of memory access rules to be applied at instances during further execution of the sequence of code; at said instances, applying said memory access rules for memory accesses by the plurality of processing elements; and in the event of a memory access by a processing element violating one or more of said rules, generating a warning, signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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Specification