MULTIPROCESSOR SYSTEM, APPARATUS AND METHODS

• US 20130262806A1
• Filed: 11/30/2012
• Published: 10/03/2013
• Est. Priority Date: 03/30/2012
• Status: Active Grant

• Current Assignee: U-Blox AG (u-blox Holding AG)
• Original Assignee: Erkut Uygun
• Inventors: Tindall, Paul, Uygun, Erkut
• Granted Patent: US 9,600,422 B2
• Time in Patent Office: Days
• US Class Current: 711/163
• CPC Class Codes: G06F 11/3409 for performance assessment
• CPC Class Codes: G06F 11/3471 Address tracing
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program
• CPC Class Codes: G06F 12/1458 by checking the subject access rights
• CPC Class Codes: G06F 8/4442 Reducing the number of cache misses; Data prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/30185 according to one or more bits in the instruction, e.g. prefix, sub-opcode
• CPC Class Codes: G06F 9/45504 Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators

Abstract

Embodiments of the present invention provide methods and apparatus in a multiprocessor system, whereby a set of rules relating to memory access are created and implemented in a hardware element. The rules can be updated dynamically, for example by the sequence processor (or sequencer) used to control the multiple processing elements.

Claims

1. A method in a multiprocessor system, the system comprising a plurality of processing elements, memory to which each of the processing elements has access, and a sequencer adapted to generate a sequence of code to be executed by the plurality of processing elements, the method comprising:

receiving a plurality of signals during execution of the sequence of code, the signals indicating a plurality of memory access rules to be applied at instances during further execution of the sequence of code;

at said instances, applying said memory access rules for memory accesses by the plurality of processing elements; and

in the event of a memory access by a processing element violating one or more of said rules, generating a warning, signal.

2. The method according to claim 1, wherein the plurality of signals includes one or more signals indicating one or more memory addresses and the expected data contents at those one or more memory addresses.

3. The method according to claim 1, wherein the plurality of signals includes one or more signals indicating a particular memory address and a processing element which is expected to access the particular memory address.

4. The method according to claim 1, further comprising:

on generation of the warning signal, taking action to handle the consequences of the one or more rule violations.

5. The method according to claim 4, wherein said action comprises one or more of:

halting execution of part or all of the sequence of code;

outputting trace data of memory accesses prior to the violation; and

triggering an exception handling routine.

6. The method according to claim 1, wherein a violation is deemed to occur if a memory access by a processing element specifies a memory address to which access by the processing element is restricted.

7. The method according to claim 1, wherein a violation is deemed to occur if a memory access specifies a write action to a memory address which is read only.

8. The method according to claim 1, wherein a violation is deemed to occur if a memory access specifies a data value which differs from a value specified in one of said memory access rules.

9. The method according to claim 1, further comprising:

detecting memory accesses on one or more buses connected to said memory.

10. The method according to claim 1, wherein said plurality of signals are received from the sequencer.

11. The method according to claim 10, wherein the plurality of signals update said memory access rules dynamically as execution of the sequence of code progresses.

12. The method according to claim 1, carried out on trace data acquisition circuitry, provided for the purpose of debugging.

13. A hardware element for use in a multiprocessor system, the hardware element being adapted to perform the method according to claim 1.

14. A multiprocessor system, comprising:

a plurality of processing elements;

memory to which each of the processing elements has access;

a sequencer adapted to generate a sequence of code to be executed by the plurality of processing elements; and

a hardware element as claimed in claim 13.