APPARATUS AND METHOD FOR A REDUCED PIN COUNT (RPC) MEMORY BUS INTERFACE INCLUDING A READ DATA STROBE SIGNAL

• US 20130262907A1
• Filed: 03/30/2012
• Published: 10/03/2013
• Est. Priority Date: 03/30/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies Batam PT (Infineon Technologies AG)
• Original Assignee: Clifford Alan Zitlaw
• Inventors: ZITLAW, Clifford Alan
• Granted Patent: US 8,966,151 B2
• Time in Patent Office: Days
• US Class Current: 713/501
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 1/22 Means for limiting or controlling the pin/gate ratio

Abstract

A method and apparatus for a memory bus interface including a read data strobe. The interface includes a chip select for delivering a chip select signal that indicates when a peripheral device is activated, wherein said bus interface provides communication between a host device and said peripheral device. The interface also includes a differential clock pair for delivering a differential clock signal. A read data strobe is included in the interface for delivering a read data strobe signal from the peripheral device. The interface includes a data bus for delivering command, address, and data information. The read data strobe indicates when valid data is present on the data bus.

Claims

1. A memory bus interface, comprising:

a chip select for delivering a chip select signal indicating when a peripheral device is activated, wherein said bus interface provides communication between a host device and said peripheral device;

a differential clock pair for delivering a differential clock signal comprising a first clock signal and a second clock signal;

a read data strobe for delivering a read data strobe signal from said peripheral device; and

a data bus for delivering command, address, and data information.

2. The memory bus interface of claim 1, wherein said pair of differential clocks and said read data strobe enable transfer of data in a Double Data Rate (DDR) manner.

3. The memory bus interface of claim 1, wherein said data bus comprises an 8 line wide data bus, and said memory bus interface comprises a 12 line interface.

4. The memory bus interface of claim 1, wherein in a read transaction, crossings of said differential clock pair indicate delivery of said command and said address information, and transitions of said read data strobe signal indicate delivery of said data information.

5. The memory bus interface of claim 1, wherein in a write transaction, crossings of said differential clock pair indicate delivery of said command, address, and data information.

6. The memory bus interface of claim 1, wherein a functionality of said clock pair is single ended or differential.

7. The memory bus interface of claim 1, wherein a functionality of said read data strobe is single ended or differential.

8. The memory bus interface of claim 1, wherein said data bus operates as a single data rate bus or a double data rate bus.

9. A method for performing transactions using a memory bus interface, comprising:

configuring a chip select to facilitate delivery of a chip select signal indicating when a peripheral device is activated, wherein said bus interface provides communication between a host device and said peripheral device;

configuring a differential clock pair for delivering a first clock signal and a second clock signal to enable a differential clock signal;

configuring a read data strobe for delivering a source synchronous output clock as a read data strobe signal from said peripheral device; and

configuring a data bus for delivering command type, address, and data information;

wherein said pair of differential clocks and said read data strobe enable transfer of data in a Double Data Rate (DDR) manner for a read transaction and a write transaction.

10. The method of claim 9, further comprising performing said read transaction, wherein said performing said read transaction comprises:

initiating at said host device said read transaction by asserting said chip select signal while voltages for said first clock signal and said second clock signal are LOW and HIGH;

sending a read type command and a target address over three clock cycles in said differential clock signal over said data bus, wherein said read type command indicates said transaction comprises a read type;

indicating whether said read transaction is of a continuous burst type or a wrapped burst type;

receiving data at said host device from said peripheral device over said data bus;

receiving at said host device a read data strobe signal over said read data strobe

retrieving at said host device said data beginning with a leading edge of said read data strobe signal, wherein said read data strobe signal comprises a source synchronous output clock.

11. The method of claim 10, further comprising:

sending said read command and said target address over six clock transitions over said data bus; and

waiting for a transition of said RDS signal before said retrieving said data.

12. The method of claim 10, further comprising;

toggling said differential clock signal and said read data strobe signal for each data value in a multi-byte burst mode.

13. The method of claim 10, further comprising:

terminating said read transaction by asserting said chip select signal to HIGH while said first clock signal is LOW and said second clock signal is HIGH.

14. The method of claim 10, further comprising:

triggering said read data strobe signal at said peripheral device as soon as said data is ready.

15. The method of claim 9, further comprising performing said write transaction, where said performing write transaction comprises:

indicating at said host device a beginning of said write transaction by transitioning said chip select to LOW while said first clock signal is LOW and said second clock signal is HIGH;

sending a write type command and a target address over three clock cycles in said differential clock signal over said data bus, wherein said write type command indicates said transaction comprises a write type;

indicating whether said write transaction is of a continuous burst type or a wrapped burst type; and

sending data from said host device over said data bus.

16. The method of claim 15, further comprising:

center aligning said command, address and data information with signal crossings of said first and second clock signals.

17. The method of claim 15, further comprising:

toggling said differential clock signal for each data value in a multi-byte burst mode.

18. The method of claim 15, further comprising:

terminating said write transaction by asserting said chip select signal to HIGH while said first clock signal is LOW and said second clock signal is HIGH.

19. An apparatus, comprising:

a host device;

a memory device comprising a memory array operable for storing data;

a processor; and

a bus interface providing connectivity between said memory device and said host device, wherein said bus interface comprises;

a chip select for delivering a chip select signal indicating when a peripheral device is activated, wherein said bus interface provides communication between a host device and said peripheral device;

a differential clock pair for delivering a differential clock signal comprising a first clock signal and a second clock signal;

a read data strobe for delivering a read data strobe signal from said peripheral device; and

a data bus for delivering command, address, and data information.

20. The apparatus of claim 19, wherein said read data strobe indicates the delivery of read data information.