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APPARATUS AND METHOD FOR A REDUCED PIN COUNT (RPC) MEMORY BUS INTERFACE INCLUDING A READ DATA STROBE SIGNAL

  • US 20130262907A1
  • Filed: 03/30/2012
  • Published: 10/03/2013
  • Est. Priority Date: 03/30/2012
  • Status: Active Grant
First Claim
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1. A memory bus interface, comprising:

  • a chip select for delivering a chip select signal indicating when a peripheral device is activated, wherein said bus interface provides communication between a host device and said peripheral device;

    a differential clock pair for delivering a differential clock signal comprising a first clock signal and a second clock signal;

    a read data strobe for delivering a read data strobe signal from said peripheral device; and

    a data bus for delivering command, address, and data information.

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