CONTROL OF BEVEL ETCH FILM PROFILE USING PLASMA EXCLUSION ZONE RINGS LARGER THAN THE WAFER DIAMETER

• US 20130264015A1
• Filed: 03/11/2013
• Published: 10/10/2013
• Est. Priority Date: 01/26/2007
• Status: Active Grant

• Current Assignee: Lam Research Corporation
• Original Assignee: Lam Research Corporation
• Inventors: Fang, Tong, Kim, Yunsang, Kim, Keechan, Stojakovic, George
• Granted Patent: US 10,629,458 B2
• Time in Patent Office: Days
• US Class Current: 156/345.48
• CPC Class Codes: H01J 37/32642 Focus rings
• CPC Class Codes: H01L 21/02087 Cleaning of wafer edges
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/67028 for cleaning followed by drying, rinsing, stripping, blasting or the like

Abstract

A method of cleaning a bevel edge of a semiconductor substrate is provided. A semiconductor substrate is placed on a substrate support in a reaction chamber of a plasma processing apparatus. The substrate has a dielectric layer overlying a top surface and a bevel edge of the substrate, the layer extending above and below an apex of the bevel edge. A process gas is introduced into the reaction chamber and energized into a plasma. The bevel edge is cleaned with the plasma so as to remove the layer below the apex without removing all of the layer above the apex.

Claims

1. (canceled)

2. (canceled)

3. (canceled)

4. (canceled)

5. (canceled)

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11. (canceled)

12. A bevel etcher wherein a bevel edge of a semiconductor wafer is subjected to plasma cleaning, comprising:

a lower support having a cylindrical top portion;

a lower plasma-exclusion-zone (PEZ) ring supported on the top portion of the lower support, the lower PEZ ring having an upper surface on which the wafer is supported;

an upper dielectric component disposed above the lower support and having a cylindrical bottom portion opposing the top portion of the lower support;

an upper PEZ ring surrounding the bottom portion of the dielectric component and opposing the lower PEZ ring, an annular space between the lower and upper PEZ rings limiting the extent of the bevel edge to be cleaned by the plasma; and

at least one radio frequency (RF) power source adapted to energize process gas into the plasma during a cleaning operation;

wherein the lower and upper PEZ rings are adapted to respectively shield the lower support and the upper dielectric component from the plasma during the cleaning operation; and

wherein a portion of the upper PEZ ring closest to the wafer has an outer diameter at least equal to an outer diameter of the wafer.

13. The bevel etcher of claim 12, wherein the wafer is a 300 mm diameter wafer and the portion of the upper PEZ ring closest to the wafer has an outer diameter 0.5 mm to 5 mm larger than the outer diameter of the wafer.

14. The bevel etcher of claim 12, wherein the lower PEZ ring has an upper surface on which the wafer is supported such that the bevel edge of the substrate extends outwardly of an outer edge of the upper surface.

15. A configurable part of a bevel etcher wherein a bevel edge of a semiconductor wafer is subjected to plasma cleaning, the bevel etcher including a lower electrode assembly on which the wafer is supported during the bevel cleaning operation, an upper electrode assembly including a dielectric plate facing the lower support and attached to an upper support which is movable vertically to position the dielectric plate at a small distance from the upper surface of the wafer, the upper electrode assembly including at least one gas passage through which gas can be flowed in the vicinity of the bevel edge during the bevel cleaning operation, the dielectric plate having at least one gas passage through which gas can be flowed over the surface of the wafer during the bevel cleaning operation, the configurable part comprising an upper PEZ ring of electrically conductive, semiconductive or dielectric material adapted to shield the upper dielectric plate from the plasma during the cleaning operation, a portion of the upper PEZ ring closest to the wafer having an outer diameter which is greater than the outer diameter of the wafer.

16. The configurable part of claim 15, wherein the upper PEZ ring includes an inner flange having a lower surface thereof engaging an upper surface of an outer flange on the dielectric plate such that when mounted in the bevel etcher an annular space is formed between the lower and upper PEZ rings limiting the extent of the bevel edge to be cleaned by the plasma.

17. The configurable part of claim 15, wherein the upper PEZ ring includes a stepped inner surface extending vertically between upper and lower surfaces thereof, the upper and lower surfaces being parallel to each other.

18. The configurable part of claim 15, wherein the upper PEZ ring includes an outer surface which is stepped such that an open space overlies the wafer when the substrate is supported on the lower PEZ ring.

19. The configurable part of claim 15, wherein the portion of the upper PEZ ring closest to the wafer has an outer diameter 0.5 mm to 5 mm larger than the outer diameter of the wafer.