ADJUSTING REFERENCE RESISTANCES IN DETERMINING MRAM RESISTANCE STATES

• US 20130265820A1
• Filed: 04/10/2012
• Published: 10/10/2013
• Est. Priority Date: 04/10/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: CHIH, Yue-Der, LIN, Chun-Jung, LIN, Kai-Chun, YU, Hung-Chang, HUANG, Chin- Yi
• Granted Patent: US 8,902,641 B2
• Time in Patent Office: Days
• US Class Current: 365/158
• CPC Class Codes: G11C 11/15 using multiple magnetic layers G11C11/155 takes precedence
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods

Abstract

Magneto-resistive memory bit cells in an array have high or low resistance states storing logic values. During read operations, a bias source is coupled to an addressed memory word, coupling a parameter related to cell resistance to a sense amplifier at each bit position. The sense amplifiers determine whether the parameter value is greater or less than a reference value between the high and low resistance states. The reference value is derived by averaging or splitting a difference of resistances of reference cells at high and/or low resistance states. Bias current is conducted over address lines with varying resistance, due to different distances between the sense amplifiers and addressed memory words, which is canceled by inserting into the comparison circuit a resistance from a dummy addressing array, equal to the resistance of the conductor addressing the selected word line and bit position.

Claims

1. A digital memory, comprising:

an array of magnetoresistive memory bit cells, each of the bit cells comprising at least one magnetic tunnel junction element having at least two magnetic layers in a stack including a pinned layer with a permanent magnetic field establishing a reference direction, and a free layer with a magnetic field component that is selectively alignable parallel to the reference direction, thereby providing a state of low electrical resistance through the stack, and anti-parallel to the reference direction, thereby providing a state of high electrical resistance through the stack;

a current bias source for supplying a current to at least a selected one of the bit cells coupled to a comparison circuit for comparing a resistance related parameter of the at least one magnetic tunnel junction element of the selected bit cell to a reference for distinguishing between the high and low resistance states;

wherein the reference is based on at least one of a resistance of plural associated magnetic tunnel junction elements, and a resistance determined by a location of the selected bit cell in the array.

2. The digital memory of claim 1, wherein the reference is derived from plural reference magnetic tunnel junction elements on a same circuit with the array of bit cells, the plural reference magnetic tunnel junction elements having high and low resistance states contributing to the reference.

3. The digital memory of claim 1, wherein reference is derived from a reference resistance plus an offset resistance that is variable with a length of at least one conductor coupling one of the reference resistance and the selected bit cell to at least one of a bias source and a sense amplifier.

4. The digital memory of claim 2, wherein the at least one additional magnetic tunnel junction element comprises plural magnetic tunnel junction elements that are all in one of a high resistance state and a low resistance state, and the reference resistance is at least partly a function of an average of resistances in at least one of the states.

5. The digital memory of claim 2, wherein the reference is provided by a reference circuit comprising plural magnetic tunnel junction elements, some of which magnetic tunnel junction elements are in their high resistance state and other are in their low resistance state, wherein the reference resistance is at least partly a function of one of an average resistance and a parallel resistance of plural resistances of magnetic tunnel junction elements in each of the two states.

6. The digital memory of claim 2, wherein the reference is provided by a reference circuit having groups of plural magnetic tunnel junction elements that are in their high resistance states and their the low resistance states, respectively, and wherein the reference resistance is at least partly a function of values in both of said states.

7. The digital memory of claim 6, wherein the values for at least one of the high and low resistance states are based on an average resistance of the plural magnetic junction elements of at least one of the groups.

8. The digital memory of claim 6, wherein the values for at least one of the high and low resistance states are based on a parallel resistance of the plural magnetic junction elements of at least one of the groups.

9. A digital memory, comprising:

an array of magnetoresistive memory bit cells, each of the bit cells comprising at least one magnetic tunnel junction element having at least two magnetic layers in a stack including a pinned layer with a permanent magnetic field establishing a reference direction, and a free layer with a magnetic field component that is selectively alignable parallel to the reference direction, thereby providing a state of low electrical resistance through the stack, and anti-parallel to the reference direction, thereby providing a state of high electrical resistance through the stack;

a current bias source for supplying a current to at least a selected one of the bit cells;

an addressing circuit having a plurality of conductors for individually coupling at least one magnetic junction element of each of the bit cells to the current bias source;

a comparison circuit for comparing a resistance of the at least one magnetic tunnel junction element of the selected bit cell to a reference resistance;

wherein at least one of a high resistance value and a low resistance value of a circuit including the magnetic junction element, the addressing circuit and the comparison circuit varies with a location of the at least one magnetic tunnel junction element in the array of bit cells; and

,

wherein the reference resistance is varied with the location of the magnetic tunnel junction element in the array of bit cells.

10. The digital memory of claim 9, wherein the conductors of the addressing circuit have resistances that vary with said location of the magnetic tunnel junction element in the array of bit cells, and further comprising an offsetting resistance coupled in to the comparison circuit that at least partly cancels variation in the resistances with said location.

11. The digital memory of claim 10, further comprising a comparison addressing circuit for providing said offsetting resistance, the comparison addressing circuit having addressed resistances that substantially model resistances of the conductors of the addressing circuit, and wherein the comparison circuit is configured to compare a resistance of a magnetic tunnel junction element in a bit cell as addressed through the addressing circuit against a sum of a predetermined reference resistance and one of the addressed resistances of the comparison addressing circuit.

12. The digital memory of claim 11, wherein the predetermined reference resistance comprises a fixed resistance.

13. The digital memory of claim 11, wherein the predetermined reference resistance comprises a plurality of resistances that vary with location in the array.

14. The digital memory of claim 9, wherein the magnetic tunnel junction elements in the array of bit cells are subject to manufacturing variations that produce differences in resistance of at least one of the high and low resistance states of the magnetic junction elements at differing locations in the array, and wherein the predetermined reference resistance used for comparison against the resistance state of at least one magnetic tunnel junction in a bit cell at a given location in the array is based on resistances of other magnetic tunnel junction elements at locations near to the given location.

15. The digital memory of claim 14, wherein the other magnetic tunnel junction elements at locations near to the given location comprise plural magnetic tunnel junction elements that are all in one of a high resistance state and a low resistance state, and the reference resistance is at least partly a function of an average of resistances in at least one of the states.

16. The digital memory of claim 14, wherein the other magnetic tunnel junction elements at locations near to the given location comprise two groups of plural magnetic tunnel junction elements that are in their high resistance states and their the low resistance states, respectively, and wherein the reference resistance is at least partly a function of values in both of said states that are one of averaged and determined as parallel resistance values.

17. The digital memory of claim 16, further comprising at least one current summing transistor coupled to a plurality of said magnetic tunnel junction elements through respective addressing conductors coupled to a current source, and wherein the reference resistance is based at least partly on a current conducted through the summing transistor.

18. The digital memory of claim 14, further comprising at least one current mirror transistor coupled to a plurality of said magnetic tunnel junction elements through respective addressing conductors coupled to a current source, and wherein the reference resistance is based at least partly on a current conducted through the current mirror transistor.

19. A method for discriminating between high and low resistance states of memory bits in a magneto-resistive memory, comprising:

providing an array of bit cell magnetic terminal junction elements arranged as addressable words of bit cells at bit cell positions;

during a read operation, addressably selecting the bit cell magnetic terminal junction elements in an addressable word for coupling the bit cells of the word to a source of bias current and to a sense amplifier for each said bit position, the sense amplifier at each bit position being configured to effect a comparison of a resistance related parameter of a respective said bit cell versus a reference value;

coupling a reference level to the sense amplifier as said reference value and reading out a logic value of the bit cell from an output of the sense amplifier;

wherein the reference level is affected by one of averaging an effect of at least two reference magnetic terminal junctions, and inserting an addressing conductor of a dummy conductor array when coupling the reference level to the sense amplifier, the addressing conductor of the dummy conductor array substantially offsetting a resistance of conductors addressing the selected bit cell.

20. The method of claim 19, wherein the reference level is affected by both of averaging the effect of at least two reference magnetic terminal junctions, and inserting an addressing conductor of a dummy conductor array when coupling the reference level to the sense amplifier, substantially offsetting a resistance of conductors addressing the selected bit cell.